公开(公告)号：US20170365504A1

公开(公告)日：2017-12-21

申请号：US15186640

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming conductive interconnects in an ILD including a high etch selectivity dielectric layer such as a silicon nitride with hydrogen component (SiNH) layer, and patterning an air gap mask layer preferably using extreme ultraviolet (EUV) light form an air gap mask. The air gap mask may be used to etch an air gap space in the high etch selectivity dielectric layer. Use of EUV with the high etch selectivity dielectric layer provides an air gap having a width of no greater than 15 nm with the opening used to form the air gap space having a width of no greater than 10 nm width. This integration approach offers smaller pinch-off height, e.g., less than approximately 6 nm, which improves process window for subsequent Mx+1 module builds.

公开(公告)号：US20160370421A1

公开(公告)日：2016-12-22

申请号：US14743208

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: G01R31/26 ,  G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L22/12 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/34

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Abstract translation: 半导体器件包括第一电路结构和第二电路结构。 第一电路结构包括在布线和电接触布线之间的布线和通孔。 该通孔在布线的表面上的通孔下方的通孔和布线之间引起横向蚀刻空隙。 第二电路结构包括相对于参考布线的类似的布线，没有或更少的通孔。 因此，与第二电路结构相比，第一电路结构相对更倾向于侧向蚀刻空隙形成。 在第一电路结构和第二电路结构上测量电阻，并与比较阈值进行比较，以确定第一电路结构是否包括一个或多个横向蚀刻空隙。 如果第一结构被认为不包括侧向蚀刻空隙，则该装置的制造过程可以被认为是可靠的。

公开(公告)号：US09425144B2

公开(公告)日：2016-08-23

申请号：US14580539

申请日：2014-12-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali Lustig ,  Andrew H. Simon ,  Junjing Bao

IPC: H01L21/44 ,  H01L23/525 ,  H01H69/02 ,  H01H85/046 ,  H01L23/522 ,  H01L23/528 ,  H01H85/02

CPC classification number: H01L23/5256 ,  H01H69/02 ,  H01H85/046 ,  H01H2085/0275 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

公开(公告)号：US20180076082A1

公开(公告)日：2018-03-15

申请号：US15813399

申请日：2017-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

公开(公告)号：US09461017B1

公开(公告)日：2016-10-04

申请号：US14685061

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Andrew H. Simon ,  Anthony K. Stamper

IPC: H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/66 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/8112 ,  H01L2224/8312 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14

Abstract: An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is provided. The electronic package also includes a first bonding layer coupling one side of the first IC device entirely to a portion of a side of the second IC device. The remaining portion of the side of the second IC device that is not coupled to the one side of the first IC device, includes an antenna.

Abstract translation: 提供了一种包括多个垂直堆叠集成电路（IC）装置的电子封装，包括第一IC器件和第二IC器件。 电子封装还包括将第一IC器件的一侧完全耦合到第二IC器件的一侧的一部分的第一接合层。 第二IC器件的未耦合到第一IC器件的一侧的侧面的剩余部分包括天线。

公开(公告)号：US20150061135A1

公开(公告)日：2015-03-05

申请号：US14538944

申请日：2014-11-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronic Corporation ,  STMICROELECTRONICS, INC.

Inventor： Frieder H. Baumann ,  Tibor Bolom ,  Chao-Kun Hu ,  Koichi Motoyama ,  Chengyu Niu ,  Andrew H. Simon

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Abstract translation: 具有位于邻近侧壁的扩散阻挡层的结构和在介电材料层中蚀刻的开口的底部。 该结构还具有直接位于扩散阻挡层顶部的金属衬垫，直接位于金属衬垫顶部上的种子层，其中种子层由包括铜的材料制成，铜材料直接位于种子顶部 层，直接位于铜材料的顶部和选择性上的金属盖，以及直接位于金属盖的顶部并且邻近金属盖的封盖层。

公开(公告)号：US10224236B2

公开(公告)日：2019-03-05

申请号：US15813399

申请日：2017-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

公开(公告)号：US20170236780A1

公开(公告)日：2017-08-17

申请号：US15485657

申请日：2017-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Shishir K. Ray ,  Andrew H. Simon ,  Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Michael P. Chudzik

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252

Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

公开(公告)号：US20170213792A1

公开(公告)日：2017-07-27

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US09601513B1

公开(公告)日：2017-03-21

申请号：US14977899

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Terence B. Hook ,  Andreas Scholze ,  Lars W. Liebmann ,  Roger A. Quon ,  Andrew H. Simon

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/84 ,  H01L21/845 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649

Abstract: Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.