公开(公告)号：US20200212192A1

公开(公告)日：2020-07-02

申请号：US16238173

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Julien FROUGIER ,  Chanro PARK ,  Kangguo CHENG

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

Abstract: A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.

公开(公告)号：US20190279910A1

公开(公告)日：2019-09-12

申请号：US15914547

申请日：2018-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Stan TSAI

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L27/088 ,  H01L29/45 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

公开(公告)号：US20160254158A1

公开(公告)日：2016-09-01

申请号：US14634483

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-Gyu SUNG ,  Chanro PARK ,  Ruilong XIE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

Abstract translation: 共同制造具有不同阈值电压的非平面（即，三维）半导体器件包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，至少两个栅极结构， 每个栅极结构包括一个衬有介电材料并部分填充有功函材料的栅极开口，一部分功函材料被凹入。 共同制造还包括在一个或多个且少于所有的栅极开口中产生至少一个共形阻挡层，用导电材料填充栅极开口，以及修改至少一个且小于所有填充的栅极开口的功函数 门结构。

公开(公告)号：US20200098913A1

公开(公告)日：2020-03-26

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Andre LABONTE ,  Daniel CHANEMOUGAME

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US20190088764A1

公开(公告)日：2019-03-21

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Steven BENTLEY ,  Puneet Harischandra SUVARNA ,  Chanro PARK ,  Min Gyu SUNG ,  Lars LIEBMANN ,  Su Chen FAN ,  Brent ANDERSON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20180138279A1

公开(公告)日：2018-05-17

申请号：US15351893

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Lars Wolfgang LIEBMANN ,  Hoon KIM

IPC: H01L29/417 ,  H01L29/772 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US20180130889A1

公开(公告)日：2018-05-10

申请号：US15345137

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/45 ,  H01L29/665

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20170256455A1

公开(公告)日：2017-09-07

申请号：US15599026

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20160307807A1

公开(公告)日：2016-10-20

申请号：US14691233

申请日：2015-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kwan-Yong LIM ,  Steven John BENTLEY ,  Chanro PARK

IPC: H01L21/8238 ,  H01L21/225 ,  H01L29/10 ,  H01L21/308 ,  H01L29/167 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract translation: 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.