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    Method of fabricating planar dielectric isolated integrated circuits
    1.
    发明授权
    Method of fabricating planar dielectric isolated integrated circuits 失效
    制造平面电介质隔离集成电路的方法

    公开(公告)号：US3575740A

    公开(公告)日：1971-04-20

    申请号：US3575740D

    申请日：1967-06-08

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  MASON JOHN W

    IPC: H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L7/36 ,  H01L3/00

    CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/76297 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S438/945 ,  Y10S438/977

    Abstract: A METHOD FOR FABRICATING DIELECTRIC ISOLATED INTEGRATED DEVICES WHICH ALLOWS THE OF FORMATION OF A TRULY PLANAR SURFACE. THE METHOD INCLUDES ETCHING ISOLATION CHANNELS IN A SEMICONDUCTOR SUBSTRATE THROUGH A SUITABLE MASK. THE MASK PATTERN IS DESIGNED TO ENHANCE DEEPER ETCHING AT CERTAIN LOCATIONS IN THE ISOLATION CHANNELS. A DIELECTRIC LAYER IS FORMED OVER THE EXPOSED SURFACES OF THE ISOLATION CHANNELS AND A SEMICONDUCTOR MATERIAL IS GROWN IN THE CHANNELS. THE DEEPER ETCHED LOCATIONS WHICH ARE NOW FILLED WITH DIELECTRIC ISOLATION ARE USED AS A DEPTH GUIDE IN THE FORMATION OF A DIELECTRIC LAYER FROM THE SEMICONDUCTOR SUBSTRATE SURFACE OPPOSITE TO THE ONE FROM WHICH THE ETCHING TOOK PLACE. THE DEPTH GUIDE CAN BE USED IN EITHER A DEEP ETCH OR LAP-BACK PROCESS. THE LAST ISOLATION STEP IS THEN TO CONTINUE THE DIELECTRIC LAYER PAST THE DEPTH GUIDE TO THE MAJOR PORTION OF TSHE ISOLATION CHANNELS TO PRODUCE THE FULLY ISOLATED ISLANDS OF SEMICONDUCTOR MATERIAL IN THE SEMICONDUCTOR SUBSTRATE.

    Abstract translation: 一种用于制造绝缘隔离集成器件的方法，其允许形成真正平坦的表面。 该方法包括通过合适的掩模蚀刻半导体衬底中的隔离通道。 掩模图案被设计为在隔离通道中的某些位置增强更深刻的蚀刻。 在隔离通道的暴露表面上形成电介质层，并且在通道中生长半导体材料。 现在填充介电隔离的较深的蚀刻位置被用作从与蚀刻发生的相反的半导体衬底表面形成电介质层的深度引导。 深度指导可用于深刻蚀或回圈过程。 然后，最后一个隔离步骤是使绝缘层继续穿过隔离通道的主要部分的深度导向，以在半导体衬底中产生完全隔离的半导体材料岛。

    Metallization process
    6.
    发明授权
    Metallization process 失效
    金属化过程

    公开(公告)号：US3558352A

    公开(公告)日：1971-01-26

    申请号：US3558352D

    申请日：1966-10-27

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  WITT DAVID DE ,  MUTTER WALTER E ,  DHAKA VIR A

    IPC: H01L21/00 ,  H01L21/331 ,  H01L23/485 ,  H01L29/00 ,  H01L1/14 ,  H01L5/02

    CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L29/00 ,  H01L29/66303 ,  H01L2924/0002 ,  Y10S438/951 ,  H01L2924/00

    Abstract: A SEMICONDUCTIVE DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE WHEREIN THE OHMIC CONTACT IS IN THE ORDER OF MICRONS IN WIDTH. A FIRST METAL IS FORMED IN THE OPENING IN THE PROTECTIVE COATING WHICH ACTS AS THE OHMIC CONTACT TO THE SEMICONDUCTOR DEVICE. A SECOND METAL MAY BE APPLIED ONLY OVER THE FIRST METAL BY ELECTROLESS OR ELECTROPLATING TECHNIQUES TO INCREASE THE CONDUCTIVITY OF THE OHMIC CONTACT. FINALLY, AN EXTERNAL LAND METAL LAYER IS DEPOSITED OVER A RELATIVELY LARGE AREA OF THE PROTECTIVE COATING IN THE AREA OF THE OHMIC CONTACT WITH FINGER-LIKE EXTENSIONS OF THE LAND METAL LAYER CONTACTING THE OHMIC CONTACT BY SHORT OVERLAID AREAS. THE EXTERNAL LAND IS THE ONLY METAL LAYER IN THE PROCESS FORMED WHICH REQUIRES A PHOTOGRAPHIC MASK. THE PROCESS, THEREFORE, IN NOT LIMITED BY PRESENT DAY PHOTOENGRAVING TECHNIQUES.

    Method of making a common emitter transistor integrated circuit structure
    9.
    发明授权
    Method of making a common emitter transistor integrated circuit structure 失效
    制造公共发射极晶体管集成电路结构的方法

    公开(公告)号：US3865648A

    公开(公告)日：1975-02-11

    申请号：US42575473

    申请日：1973-12-10

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

    IPC: H01L21/761 ,  H01L27/00 ,  H01L7/36 ,  B01J17/00 ,  H01L29/72

    CPC classification number: H01L21/761 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151

    Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

    Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

    Common emitter transistor integrated circuit structure
    10.
    发明授权
    Common emitter transistor integrated circuit structure 失效
    共同发光二极管集成电路结构

    公开(公告)号：US3648130A

    公开(公告)日：1972-03-07

    申请号：US3648130D

    申请日：1969-07-16

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  GROCHOWSKI EDWARD G ,  NORTH WILLIAM D ,  PALFI THOMAS L

    IPC: F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

    CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

    Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN- or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

    Abstract translation: 一种平面集成半导体电路，其具有通过发射极区彼此隔离并且与其它晶体管隔离的共同发射极晶体管元件，其与形成集成电路的半导体元件的主体形成PN或整流结。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

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