公开(公告)号：US20210143265A1

公开(公告)日：2021-05-13

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US09932671B2

公开(公告)日：2018-04-03

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Patricio E. Romero ,  Scott B. Clendenning ,  Grant M. Kloster ,  Florian Gstrein ,  Harsono S. Simka ,  Paul A. Zimmerman ,  Robert L. Bristol

IPC: H01L21/336 ,  C23C16/455 ,  C23C16/18 ,  C23C16/48 ,  H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L21/033

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

公开(公告)号：US20250112077A1

公开(公告)日：2025-04-03

申请号：US18478391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Andrey Vyatskikh ,  Adel Elsherbini ,  Brandon M. Rawlings ,  Tushar Kanti Talukdar ,  Thomas L. Sounart ,  Kimin Jun ,  Johanna Swan ,  Grant M. Kloster ,  Carlos Bedoya Arroyave

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.

公开(公告)号：US20250105046A1

公开(公告)日：2025-03-27

申请号：US18473905

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Andrey Vyatskikh ,  Carlos Bedoya Arroyave ,  Kimin Jun ,  Shawna M. Liff ,  Grant M. Kloster ,  Richard F. Vreeland ,  William P. Brezinski ,  Johanna Swan

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US20200020786A1

公开(公告)日：2020-01-16

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/265 ,  H01L29/51 ,  H01L29/775

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10971600B2

公开(公告)日：2021-04-06

申请号：US16517220

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10396176B2

公开(公告)日：2019-08-27

申请号：US15506101

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/49 ,  H01L21/265 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US09530733B2

公开(公告)日：2016-12-27

申请号：US14909736

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  James M. Blackwell ,  Scott B. Clendenning ,  Florian Gstrein ,  Eungnak Han ,  Grant M. Kloster ,  Jeanette M. Roberts ,  Patricio E. Romero ,  Rami Hourani

IPC: H01L23/58 ,  H01L23/528 ,  H01L21/32 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US20250108459A1

公开(公告)日：2025-04-03

申请号：US18478770

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Andrey Vyatskikh ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Thomas L. Sounart ,  Jeffery D. Bielefeld ,  Grant M. Kloster ,  Carlos Bedoya Arroyave ,  Golsa Naderi ,  Adel Elsherbini

IPC: B23K26/40 ,  B23K26/53 ,  B23K101/40 ,  B23K103/00

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.

公开(公告)号：US11532724B2

公开(公告)日：2022-12-20

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.