公开(公告)号：US12127363B2

公开(公告)日：2024-10-22

申请号：US17033401

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Feifei Cheng ,  Thomas Boyd ,  Kuang Liu ,  Steven A. Klein ,  Daniel Neumann ,  Mohanraj Prabhugoud

IPC: H05K7/10 ,  H01R12/52

CPC classification number: H05K7/1069 ,  H01R12/523

Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.

公开(公告)号：US11569596B2

公开(公告)日：2023-01-31

申请号：US16833221

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Kuang Liu ,  Srikant Nekkanty ,  Feroz Mohammad ,  Donald Tiendung Tran ,  Srinivasa Aravamudhan ,  Hemant Mahesh Shah ,  Alexander W. Huettis

IPC: H01R12/00 ,  H01R12/70 ,  H01R43/04

Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.

公开(公告)号：US20170176516A1

公开(公告)日：2017-06-22

申请号：US14976881

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： Mohit Mamodia ,  Kyle Yazzie ,  Dingying David Xu ,  Kuang Liu ,  Paul J. Diglio ,  Pramod Malatkar

IPC: G01R31/28 ,  H05B3/26

CPC classification number: H05B3/267 ,  G01R31/2867 ,  G01R31/2875

Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

公开(公告)号：US12009612B2

公开(公告)日：2024-06-11

申请号：US17032587

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad ,  Joe Walczyk ,  Kuang Liu ,  Zhichao Zhang

IPC: H01R13/11 ,  H05K1/02 ,  H05K9/00

CPC classification number: H01R13/11 ,  H05K1/0213 ,  H05K9/0022

Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

公开(公告)号：US10455685B1

公开(公告)日：2019-10-22

申请号：US16159840

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Kuang Liu ,  Thomas A. Boyd ,  Luis Gil Rangel ,  Muffadal Mukadem ,  Shelby A. Ferguson ,  Francis Toth, Jr. ,  Eric Buddrius ,  Ralph V. Miele ,  Sriram Srinivasan ,  Jeffory L. Smalley

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/32 ,  H05K1/02 ,  H05K3/30 ,  H01R12/70 ,  H05K7/10 ,  H01L23/367 ,  H05K3/36

Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.

公开(公告)号：US10044115B2

公开(公告)日：2018-08-07

申请号：US14757626

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Donald T. Tran ,  Gregorio Murtagian ,  Kuang Liu ,  Srikant Nekkanty ,  Feroz Mohammad ,  Karumbu Meyyappan ,  Hong Xie ,  Russell S. Aoki ,  Gaurav Chawla

IPC: H01R4/50 ,  H01R13/639 ,  H01R4/52 ,  H01R13/508 ,  H01R12/85 ,  H01R12/72

Abstract: An apparatus comprises a cable connector including: a first connector body portion including a first plurality of electrical contacts arranged to contact electrical contacts of a first surface of an edge connector substrate; a second connector body portion separate from the first connector body portion and including a second plurality of electrical contacts arranged to oppose the first plurality of electrical contacts of the first connector body portion and to contact electrical contacts of a second surface of the edge connector substrate, wherein the first and second plurality of electrical contacts are electrically coupled to one or more cables; and a joining mechanism configured to join the first connector body portion and the second connector body portion together and to apply a bias force to the edge connector substrate when the edge connector substrate is arranged between the first connector body portion and the second connector body portion.

公开(公告)号：US09603276B2

公开(公告)日：2017-03-21

申请号：US14583372

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： David J. Llapitan ,  Jeffory L. Smalley ,  Gaurav Chawla ,  Joshua D Heppner ,  Vijaykumar Krithivasan ,  Jonathan W. Thibado ,  Kuang Liu ,  Gregorio Murtagian

IPC: H01R12/00 ,  H05K7/10

CPC classification number: H05K7/1084

Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.

公开(公告)号：US11464139B2

公开(公告)日：2022-10-04

申请号：US16180499

申请日：2018-11-05

Applicant: Intel Corporation

Inventor： Kelly Lofgreen ,  Joseph Petrini ,  Todd Coons ,  Christopher Wade Ackerman ,  Edvin Cetegen ,  Yang Jiao ,  Michael Rutigliano ,  Kuang Liu

IPC: H05K7/20

Abstract: A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.

公开(公告)号：US11158969B2

公开(公告)日：2021-10-26

申请号：US15916678

申请日：2018-03-09

Applicant: Intel Corporation

Inventor： Feifei Cheng ,  Emad Al-Momani ,  Ahmet Durgun ,  Kuang Liu

IPC: H01R3/00 ,  H01R12/72 ,  H05K3/30 ,  H05K7/10 ,  H01R12/70 ,  H01R12/85 ,  H01R12/88 ,  H01R24/60 ,  H01R107/00

Abstract: Apparatuses, systems and methods associated with connector design for mating with integrated circuit packages are disclosed herein. In embodiments, a connector for mating with an integrated circuit (IC) package may include a housing with a recess to receive a portion of the IC package and a contact coupled to the housing and that extends into the recess. The contact may include a main body that extends from the housing into the recess and a curved portion that extends from an end of the main body, wherein the curved portion loops back and contacts the main body. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.