公开(公告)号：US10109940B2

公开(公告)日：2018-10-23

申请号：US15377254

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： Thomas A. Boyd ,  Feifei Cheng ,  Donald T. Tran ,  Russell S. Aoki ,  Karumbu Meyyappan

IPC: H01R12/70 ,  H01R12/88

Abstract: Embodiments herein relate to port frames and connectors for direct connections to integrated circuit packages. In various embodiments, a port frame to receive a connector and maintain a connection between the connector and a computer processor package may include a protrusion to provide stable attachment of the port frame to a bolster frame, a first wall, a second wall opposite the first wall, a first detent in the first wall, and a second detent in the second wall where the connector is to be received between the first wall and the second wall, and where the first detent is to receive a first locking protrusion extending from the connector and the second detent is to receive a second locking protrusion extending from the connector. Other embodiments may be described and/or claimed.

公开(公告)号：US10057994B2

公开(公告)日：2018-08-21

申请号：US14975352

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Thomas A. Boyd ,  Michael Z. Eckblad

IPC: H05K3/30 ,  H05K7/12 ,  H01L23/40

CPC classification number: H05K3/301 ,  H01L23/4093 ,  H01L2924/0002 ,  H05K7/12 ,  H05K2201/10325 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2924/00

Abstract: In one embodiment, a biasing device is actuated using an actuator which is aligned with the biasing device along an alignment axis. A first frame is thereby biased toward a second frame along the alignment axis to bias an integrated circuit package toward a socket. The actuator also latches the first and second frames together and biased towards each other with the integrated circuit package and the socket biased toward each other. Other aspects and features are also described.

公开(公告)号：US10418309B1

公开(公告)日：2019-09-17

申请号：US16018760

申请日：2018-06-26

Applicant: Intel Corporation

Inventor： Bijoyraj Sahu ,  Thomas A. Boyd ,  Jeffory L. Smalley

IPC: H01L23/40 ,  H01L21/48 ,  H01L23/367

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a substrate, a first die, a gasket, and a thermal interface. The first die may be connected to the substrate. The gasket may be connected to the substrate and may encircle the first die to form a space between the first die and the gasket. The thermal interface material may be located within the space formed by the first die and the gasket.

公开(公告)号：US10455685B1

公开(公告)日：2019-10-22

申请号：US16159840

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Steven A. Klein ,  Kuang Liu ,  Thomas A. Boyd ,  Luis Gil Rangel ,  Muffadal Mukadem ,  Shelby A. Ferguson ,  Francis Toth, Jr. ,  Eric Buddrius ,  Ralph V. Miele ,  Sriram Srinivasan ,  Jeffory L. Smalley

IPC: H01L23/522 ,  H01L23/485 ,  H01L23/32 ,  H05K1/02 ,  H05K3/30 ,  H01R12/70 ,  H05K7/10 ,  H01L23/367 ,  H05K3/36

Abstract: An electronic device may include a circuit board, and the circuit board may include a dielectric material. A socket may be coupled to a first side of the circuit board, and the socket may be configured to receive a semiconductor package. A backing plate may be positioned on a second side of the circuit board. A spacer may be positioned between the backing plate and the circuit board. The spacer may alter the profile of the socket to provide a curved profile to the socket. The spacer may displace a portion of the socket in a first direction, for instance when the spacer is coupled between the backing plate and the circuit board.

公开(公告)号：US20170186661A1

公开(公告)日：2017-06-29

申请号：US14998123

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Russell S. Aoki ,  Jonathan W. Thibado ,  Jeffory L. Smalley ,  David J. Llapitan ,  Thomas A. Boyd ,  Harvey R. Kofstad ,  Dimitrios Ziakas ,  Hongfei Yan

IPC: H01L23/34 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/345 ,  H01L23/4006 ,  H01L23/49816 ,  H01L23/49822 ,  H05K1/0212 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2203/176

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

公开(公告)号：US09991223B2

公开(公告)日：2018-06-05

申请号：US14975532

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Michael R. Hui ,  Jonathon R. Carstens ,  Michael S. Brazel ,  Daniel P. Carter ,  Thomas A. Boyd ,  Shelby A. Ferguson ,  Rashelle Yee ,  Joseph J. Jasniewski ,  Harvey R. Kofstad ,  Anthony P. Valpiani

IPC: B23K3/08 ,  H04L23/00 ,  H01L23/00 ,  B23K1/00 ,  B23K101/42

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/75703 ,  H01L2224/75754 ,  H01L2224/81139 ,  H01L2224/81234 ,  H01L2924/15311 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/166 ,  H05K2203/167 ,  Y02P70/613

Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.

公开(公告)号：US09859636B2

公开(公告)日：2018-01-02

申请号：US14757915

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Thomas A. Boyd ,  Jeffory L. Smalley ,  Russell S. Aoki ,  Karumbu Meyyappan

IPC: H01R12/72 ,  H01R12/70 ,  H01R13/631 ,  H01R13/635 ,  H01R13/648 ,  H01R43/26

CPC classification number: H01R12/721 ,  H01R12/7005 ,  H01R12/774 ,  H01R13/508 ,  H01R13/631 ,  H01R13/635 ,  H01R13/6485 ,  H01R43/26

Abstract: An example apparatus for connecting linear edge cards includes a housing to hold at least one set of conductive contacts facing perpendicularly towards a mating plane. The apparatus further includes an activator bar coupled to the housing, the activator bar to hold two parts of the housing apart via two opposing normal forces. The apparatus also includes a contact load spring coupled to the housing, the contact load spring to apply two forces parallel to the direction of the conductive contacts and against the two opposing normal forces of the activator bar. The apparatus further includes an ejector spring coupled to the contact load spring and the activator bar. The ejector spring is to apply a force perpendicular to the two opposing normal forces of the activator bar and in a direction of an opening of the housing.

公开(公告)号：US09743558B2

公开(公告)日：2017-08-22

申请号：US14861892

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Henry C. Bosak ,  Thomas A. Boyd ,  Harvey R. Kofstad

IPC: H01L23/427 ,  H05K7/20 ,  H01L23/40 ,  H01L23/473 ,  H01L25/065 ,  H01L23/367

CPC classification number: H05K7/20509 ,  H01L23/3672 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/473 ,  H01L25/0655 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1531 ,  H05K7/20336

Abstract: Embodiments of the present disclosure may include a heat removal assembly that is to thermally couple with two or more dice of an electronic device. The heat removal assembly may include a bellows to automatically adjust a position of at least one surface of the heat removal assembly relative to another surface of the heat removal assembly. Other embodiments may be described and/or claimed.

公开(公告)号：US20160106003A1

公开(公告)日：2016-04-14

申请号：US14861892

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Henry C. Bosak ,  Thomas A. Boyd ,  Harvey R. Kofstad

IPC: H05K7/20 ,  H05K1/02

CPC classification number: H05K7/20509 ,  H01L23/3672 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/473 ,  H01L25/0655 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1531 ,  H05K7/20336

Abstract: Embodiments of the present disclosure may include a heat removal assembly that is to thermally couple with two or more dice of an electronic device. The heat removal assembly may include a bellows to automatically adjust a position of at least one surface of the heat removal assembly relative to another surface of the heat removal assembly. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例可以包括散热组件，其与电子设备的两个或更多个骰子热耦合。 除热组件可以包括波纹管，以相对于散热组件的另一个表面自动调节散热组件的至少一个表面的位置。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10541494B2

公开(公告)日：2020-01-21

申请号：US16078613

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Donald T. Tran ,  Thomas A. Boyd ,  Yong Wang ,  Kevin J. Ceurter ,  Srikant Nekkanty ,  Russell S. Aoki ,  FeiFei Cheng

IPC: H01R13/639 ,  H01L23/32 ,  H01R12/71 ,  H01R13/627 ,  H01R13/629 ,  H01R25/00 ,  H01L23/367

Abstract: Apparatuses, methods and storage medium associated with connectors for coupling to a computer processing unit (CPU) package are disclosed herein. In embodiments, a connector assembly for connection to a computer processing unit (CPU) package may include a connector housing. One or more electrical contacts of the connector housing may be to couple to the CPU package when the connector assembly is engaged with a mating connector assembly. The connector assembly may further include a mounting handle affixed to a top of the connector housing. The mounting handle may include a locking latch that extends from the mounting handle. The locking latch may engage with a notch within the mating connector assembly that, when engaged, the locking latch may provide a force to maintain coupling of the one or more electrical contacts with the CPU package when engaged with the mating connector assembly.