公开(公告)号：US11881397B2

公开(公告)日：2024-01-23

申请号：US17869524

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Iris Moder ,  Bernhard Goller ,  Tobias Franz Wolfgang Hoechbauer ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L21/467 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L21/02203 ,  H01L21/0203 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/467 ,  H01L21/475 ,  H01L21/47576 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

公开(公告)号：US11810779B2

公开(公告)日：2023-11-07

申请号：US17841781

申请日：2022-06-16

Applicant: Infineon Technologies AG

Inventor： Sophia Friedler ,  Bernhard Goller ,  Iris Moder ,  Ingo Muri

IPC: H01L21/02 ,  H01L21/465 ,  H01L21/8258

CPC classification number: H01L21/0203 ,  H01L21/02019 ,  H01L21/465 ,  H01L21/8258

Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.

公开(公告)号：US10535553B2

公开(公告)日：2020-01-14

申请号：US15951995

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L29/41 ,  H01L21/762 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105

Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.

公开(公告)号：US10325804B2

公开(公告)日：2019-06-18

申请号：US15858875

申请日：2017-12-29

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Johannes Baumgartl ,  Iris Moder ,  Ingo Muri ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/74

Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.

公开(公告)号：US10199372B2

公开(公告)日：2019-02-05

申请号：US15631006

申请日：2017-06-23

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Iris Moder ,  Oliver Hellmund ,  Johannes Baumgartl ,  Annette Saenger ,  Barbara Eichinger ,  Doris Sommer ,  Jacob Tillmann Ludwig

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

公开(公告)号：US20180233399A1

公开(公告)日：2018-08-16

申请号：US15951995

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3105

Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.

公开(公告)号：US09960076B2

公开(公告)日：2018-05-01

申请号：US15229985

申请日：2016-08-05

Applicant: Infineon Technologies AG

Inventor： Oliver Hellmund ,  Ingo Muri ,  Johannes Baumgartl ,  Iris Moder ,  Thomas Christian Neidhart ,  Hans-Joachim Schulze

IPC: H01L29/772 ,  H01L21/762 ,  H01L21/311 ,  H01L21/306 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L21/76248 ,  H01L21/28 ,  H01L21/30608 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/764 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.

公开(公告)号：US12249504B2

公开(公告)日：2025-03-11

申请号：US17743006

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Alexander Christian Binter ,  Tobias Hoechbauer ,  Martin Huber ,  Iris Moder ,  Matteo Piccin ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/78

Abstract: pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

公开(公告)号：US12107130B2

公开(公告)日：2024-10-01

申请号：US17235989

申请日：2021-04-21

Applicant: Infineon Technologies AG

Inventor： Ingo Muri ,  Johannes Konrad Baumgartl ,  Oliver Hellmund ,  Jacob Tillmann Ludwig ,  Iris Moder ,  Thomas Neidhart ,  Gerhard Schmidt ,  Hans-Joachim Schulze

IPC: H01L29/36 ,  H01L21/02 ,  H01L21/223 ,  H01L21/225 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L29/36 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/2236 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/167

Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

公开(公告)号：US20220246745A1

公开(公告)日：2022-08-04

申请号：US17726618

申请日：2022-04-22

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Iris Moder ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Carsten von Koblinski

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L29/45

Abstract: A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.