公开(公告)号：US09530786B2

公开(公告)日：2016-12-27

申请号：US14476273

申请日：2014-09-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuang-Wen Liu

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

Abstract translation: 提供了一种包括多个门柱结构和多个介电柱的存储器件。 栅极柱结构和介电柱沿着第一方向交替地和分开地布置，并且沿第二方向交替地布置并彼此接触。 此外，栅极柱结构和电介质柱沿着第三方向嵌入堆叠层，从而将堆叠层分成多个堆叠结构。 在第二方向上的每个介电柱的侧壁和相邻的门柱结构的侧壁在第二方向上不是共面的。

公开(公告)号：US20160020295A1

公开(公告)日：2016-01-21

申请号：US14334325

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Chih Chen ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L29/45 ,  H01L29/16 ,  H01L21/283 ,  H01L29/04

CPC classification number: H01L21/76889 ,  H01L21/26506 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在半导体中形成硅化物区域。 该方法可以允许具有改善的电阻和减少的硅化物桥形成的具有硅化物层的半导体。

公开(公告)号：US11183513B1

公开(公告)日：2021-11-23

申请号：US16865442

申请日：2020-05-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Jr-Meng Wang ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

公开(公告)号：US09536808B1

公开(公告)日：2017-01-03

申请号：US14741087

申请日：2015-06-16

Applicant: Macronix International Co., Ltd.

Inventor： Zheng-Chang Mu ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0361 ,  H01L2224/05089 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract translation: 提供具有大通孔（例如焊盘下方）的半导体器件，以增加通孔开口面积比，增加通孔蚀刻速率，避免金属间电介质破裂和对集成电路的损坏。 通孔被定义为在隔离的导电底部基底层和导电顶层之间的金属间介电层中的大的开放区域。 还提供了制造具有大通孔的半导体器件的方法。

公开(公告)号：US20160247719A1

公开(公告)日：2016-08-25

申请号：US15146187

申请日：2016-05-04

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Chih Chen ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L29/792 ,  H01L21/28 ,  H01L23/532

CPC classification number: H01L21/76889 ,  H01L21/26506 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

Abstract translation: 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在半导体中形成硅化物区域。 该方法可以允许具有改善的电阻和减少的硅化物桥形成的具有硅化物层的半导体。

公开(公告)号：US09245901B1

公开(公告)日：2016-01-26

申请号：US14465598

申请日：2014-08-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuang-Wen Liu

IPC: H01L33/00 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/1052 ,  H01L21/283 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device is provided, which includes a plurality of gate pillar structures and a plurality of dielectric pillars extending alternately arranged along a same direction and embedding in a stack layer so that the stack layer divided into a plurality of stack structures.

Abstract translation: 提供了一种存储器件，其包括多个栅极柱结构和沿着相同方向交替布置并且嵌入堆叠层中的多个介电柱，使得堆叠层被分成多个堆叠结构。

公开(公告)号：US11991882B2

公开(公告)日：2024-05-21

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L29/51

CPC classification number: H10B43/27 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20220077187A1

公开(公告)日：2022-03-10

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US09384989B2

公开(公告)日：2016-07-05

申请号：US14334158

申请日：2014-07-17

Applicant: Macronix International Co., Ltd.

Inventor： Ching-Chang Lin ,  Kai-Hsiang Chang ,  Chih-Yuan Wu ,  Kuang-Wen Liu

IPC: H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

Abstract translation: 提供了一种改进的半导体器件，由此半导体器件由包括第一电介质层，设置在第一电介质层上的数据存储材料和设置在数据存储材料上的第二电介质层的分层结构限定， 半导体器件的外层。 例如，半导体器件可以是具有基本上围绕SONOS结构的氧化物 - 氧化物（ONO）膜的SONOS结构。 本发明还提供了制造本发明的半导体器件和SONOS结构的方法。

公开(公告)号：US11917828B2

公开(公告)日：2024-02-27

申请号：US17314528

申请日：2021-05-07

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Feng Liao ,  Mao-Yuan Weng ,  Kuang-Wen Liu

IPC: H10B41/00 ,  H10B43/50 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/50 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.