公开(公告)号：US20110233782A1

公开(公告)日：2011-09-29

申请号：US13052769

申请日：2011-03-21

申请人： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

发明人： Shu-Ming CHANG ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US08710680B2

公开(公告)日：2014-04-29

申请号：US13052769

申请日：2011-03-21

申请人： Shu-Ming Chang ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

发明人： Shu-Ming Chang ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC分类号： H01L29/40

CPC分类号： H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US08791768B2

公开(公告)日：2014-07-29

申请号：US13359460

申请日：2012-01-26

申请人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Wei-Chung Yang ,  Bai-Yao Lou ,  Hung-Jen Lee

发明人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Wei-Chung Yang ,  Bai-Yao Lou ,  Hung-Jen Lee

IPC分类号： H01P5/08 ,  H05K1/18

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1901 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。

公开(公告)号：US20110140267A1

公开(公告)日：2011-06-16

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/48

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US09088206B2

公开(公告)日：2015-07-21

申请号：US13359466

申请日：2012-01-26

申请人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Wei-Chung Yang ,  Bai-Yao Lou

发明人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Wei-Chung Yang ,  Bai-Yao Lou

IPC分类号： H01L29/06 ,  H01L27/06 ,  H04B1/02 ,  H02M3/155 ,  H02M3/00 ,  H01F17/00 ,  H01L23/64 ,  H01L25/16 ,  H01L23/00 ,  H01L25/07

CPC分类号： H02M3/155 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/645 ,  H01L24/16 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/16195 ,  H01L2924/19105 ,  H02M3/00

摘要： A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

摘要翻译： 电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管，通过连接层电安装在基板上。

公开(公告)号：US08431946B2

公开(公告)日：2013-04-30

申请号：US13114750

申请日：2011-05-24

申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

IPC分类号： H01L33/00

CPC分类号： H01L27/14618 ,  H01L31/048 ,  H01L2224/13 ,  H01L2933/0066 ,  Y02E10/50

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optical device disposed on the first surface; a conducting pad disposed on the first surface; a first alignment mark formed on the first surface; and a light shielding layer disposed on the second surface and having a second alignment mark, wherein the second alignment mark corresponds to the first alignment mark.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在所述第一表面上的光学装置; 设置在所述第一表面上的导电垫; 形成在第一表面上的第一对准标记; 以及遮光层，其设置在所述第二表面上并且具有第二对准标记，其中所述第二对准标记对应于所述第一对准标记。

公开(公告)号：US08604578B2

公开(公告)日：2013-12-10

申请号：US13279183

申请日：2011-10-21

申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

IPC分类号： H01L31/0203

CPC分类号： H01L27/14623 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/552 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/014

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer located on the second surface of the substrate, wherein the protection layer has an opening; a light shielding layer located on the second surface of the substrate, wherein a portion of the light shielding layer extends into the opening of the protection layer; a conducting bump disposed on the second surface of the substrate and filled in the opening of the protection layer; and a conducting layer located between the substrate and the protection layer, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 位于所述基板的第二表面上的保护层，其中所述保护层具有开口; 位于所述基板的第二表面上的遮光层，其中所述遮光层的一部分延伸到所述保护层的开口中; 设置在所述基板的第二表面上并填充在所述保护层的开口中的导电凸块; 以及位于所述衬底和所述保护层之间的导电层，其中所述导电层将所述光电器件电连接到所述导电凸块。

公开(公告)号：US20060125059A1

公开(公告)日：2006-06-15

申请号：US11012760

申请日：2004-12-15

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Bai-Yao Lou

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Bai-Yao Lou

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer includes one or more dies, each of which has a boundary surrounding an integrated circuitry for separating one from another. One or more pattern units are disposed adjacent to the die for monitoring a fabrication process thereof. A protection structure is disposed between the die and the pattern units for preventing the die from damage during a separation of the die from the semiconductor wafer. Thus, the semiconductor wafer is adapted to prevent damage during a die separation process.

摘要翻译： 半导体晶片包括一个或多个管芯，每个管芯具有围绕用于彼此分离的集成电路的边界。 一个或多个图案单元设置成与模具相邻以用于监视其制造工艺。 保护结构设置在模具和图案单元之间，用于防止模具在与半导体晶片分离期间损坏。 因此，半导体晶片适于防止在模具分离过程中的损坏。

公开(公告)号：US08384174B2

公开(公告)日：2013-02-26

申请号：US13070375

申请日：2011-03-23

申请人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

发明人： Hsin-Chih Chiu ,  Chia-Ming Cheng ,  Chuan-Jin Shiu ,  Bai-Yao Lou

IPC分类号： H01L31/0203

CPC分类号： H01L31/02164 ,  H01L27/14618 ,  H01L33/486 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/13

摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.

摘要翻译： 芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离 开口 从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。