公开(公告)号：US20240379529A1

公开(公告)日：2024-11-14

申请号：US18779664

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H10B12/00

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US20240258263A1

公开(公告)日：2024-08-01

申请号：US18631900

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L23/48

CPC classification number: H01L24/27 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/30 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06515 ,  H01L2224/275 ,  H01L2224/30181 ,  H01L2924/30105 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US20230178475A1

公开(公告)日：2023-06-08

申请号：US17832489

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun HE ,  Li-Hsien Huang ,  Yao-Chun Chuang ,  Chih-Lin Wang ,  Shih-Kang Tien

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L21/823475 ,  H01L21/823431 ,  H01L25/105

Abstract: A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third lane region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.

公开(公告)号：US20220285264A1

公开(公告)日：2022-09-08

申请号：US17470680

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US12113055B2

公开(公告)日：2024-10-08

申请号：US16907597

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Chun Chuang ,  Yu-Chen Hsu ,  Hao Chun Liu ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/10125 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

公开(公告)号：US20230045422A1

公开(公告)日：2023-02-09

申请号：US17678774

申请日：2022-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US12107041B2

公开(公告)日：2024-10-01

申请号：US18359011

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L23/5223 ,  H01L21/76843 ,  H01L23/528 ,  H01L28/40 ,  H01L28/75 ,  H01L28/84 ,  H01L28/91 ,  H10B12/033

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US11984422B2

公开(公告)日：2024-05-14

申请号：US17678774

申请日：2022-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L21/683 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L24/27 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/30 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06515 ,  H01L2224/275 ,  H01L2224/30181 ,  H01L2924/30105 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US20230290747A1

公开(公告)日：2023-09-14

申请号：US17826519

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hung Chen ,  Cheng-Pu Chiu ,  Chien-Chen Li ,  Chien-Li Kuo ,  Ting-Ting Kuo ,  Li-Hsien Huang ,  Yao-Chun Chuang ,  Jun He

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/06519 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

公开(公告)号：US09053990B2

公开(公告)日：2015-06-09

申请号：US13660441

申请日：2012-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chita Chuang ,  Yao-Chun Chuang ,  Yu-Chen Hsu ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81024 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2224/05552

Abstract: The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity.

Abstract translation: 本公开涉及一种用于制造其的装置及其方法。 该装置包括通过凸块互连结构接合到第二工件的第一工件。 凸块互连结构允许优化的包装组装产量和粘合完整性。