公开(公告)号：US09595448B2

公开(公告)日：2017-03-14

申请号：US14753735

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Shih-Ping Hong ,  Yu-Cheng Liu

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/32 ,  B08B9/08 ,  B08B7/00 ,  H01L21/67 ,  C23C16/44

CPC classification number: H01L21/02071 ,  B08B7/0035 ,  B08B9/0865 ,  C23C16/4405 ,  H01J37/3244 ,  H01J37/32834 ,  H01J37/32853 ,  H01J37/32862 ,  H01J37/32871 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02041 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76814

Abstract: A method for cleaning a plasma processing chamber is provided. The method includes introducing an organic gas into a plasma processing chamber. The organic gas includes an organic compound including carbon and hydrogen. The method includes generating an organic plasma by exciting the organic gas. The organic plasma reacts with metal compound residues over an interior surface of the plasma processing chamber to volatilize the metal compound residues into a gaseous metal compound. The method includes removing the gaseous metal compound from the plasma processing chamber.

Abstract translation: 提供了一种用于清洁等离子体处理室的方法。 该方法包括将有机气体引入等离子体处理室。 有机气体包括碳和氢的有机化合物。 该方法包括通过激发有机气体产生有机等离子体。 有机血浆与等离子体处理室的内表面上的金属化合物残留物反应，使金属化合物残留物挥发成气态金属化合物。 该方法包括从等离子体处理室中除去气态金属化合物。

公开(公告)号：US11776853B2

公开(公告)日：2023-10-03

申请号：US17646763

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Horng-Huei Tseng ,  Wen-Tung Chen ,  Yu-Cheng Liu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/823431 ,  H01L21/0217 ,  H01L21/02063 ,  H01L21/0273 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/823475 ,  H01L21/02271 ,  H01L21/823481 ,  H01L21/823821 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

公开(公告)号：US11682716B2

公开(公告)日：2023-06-20

申请号：US16902190

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US09450099B1

公开(公告)日：2016-09-20

申请号：US14743768

申请日：2015-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a protection element over the gate stack. The protection element has an upper portion and a lower portion between the upper portion and the gate stack, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a side surface of the protection element and a sidewall of the gate stack. The semiconductor device structure further includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的栅极堆叠以及栅堆叠上的保护元件。 保护元件在上部和栅极堆叠之间具有上部和下部，并且上部比下部更宽。 半导体器件结构还包括在保护元件的侧表面上的间隔元件和栅极堆叠的侧壁。 半导体器件结构还包括电连接到半导体衬底上的导电特征的导电接触。

公开(公告)号：US09355893B1

公开(公告)日：2016-05-31

申请号：US14600452

申请日：2015-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31138 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

Abstract: A method for forming an interconnect structure is provided. The method includes providing a substrate. The method also includes forming a dielectric layer on the substrate, and the dielectric layer includes an extreme low-k (ELK) dielectric layer. The method includes forming a via hole in the dielectric layer and forming a photoresist in the via hole and on the dielectric layer. The method also includes removing the photoresist by a plasma process using a CxHyOz gas and forming a conductive structure in the via hole.

Abstract translation: 提供一种形成互连结构的方法。 该方法包括提供基板。 该方法还包括在衬底上形成电介质层，并且介电层包括极低k（ELK）电介质层。 该方法包括在电介质层中形成通孔，并在通孔和电介质层上形成光致抗蚀剂。 该方法还包括通过使用C x H y O z气体的等离子体工艺去除光致抗蚀剂并在通孔中形成导电结构。

公开(公告)号：US12272595B2

公开(公告)日：2025-04-08

申请号：US17453872

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Wen-Tung Chen ,  Yu-Cheng Liu ,  Horng-Huei Tseng

IPC: H01L21/768

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

公开(公告)号：US20220130729A1

公开(公告)日：2022-04-28

申请号：US17646763

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Horng-Huei Tseng ,  Wen-Tung Chen ,  Yu-Cheng Liu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3105

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

公开(公告)号：US11217458B2

公开(公告)日：2022-01-04

申请号：US16895525

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/31 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

公开(公告)号：US09812549B2

公开(公告)日：2017-11-07

申请号：US15257567

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L29/51

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.

公开(公告)号：US09425094B2

公开(公告)日：2016-08-23

申请号：US14583238

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yungtzu Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/02186 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L2221/1063

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a hard mask layer over the dielectric layer. The method also includes performing a plasma etching process to etch the hard mask layer to form an opening, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The gas mixture has a volumetric concentration of the nitrogen-containing gas in a range from about 20% to about 30%. A volumetric concentration ratio of the carbon-containing gas to the halogen-containing gas in the gas mixture is equal to about 0.3. The method further includes etching the dielectric layer through the opening in the hard mask layer to form a feature opening in the dielectric layer. The method includes forming a conductive material in the feature opening.

Abstract translation: 提供一种形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。 该方法还包括执行等离子体蚀刻工艺以蚀刻硬掩模层以形成开口，并且在等离子体蚀刻工艺中使用的气体混合物包括含氮气体，含卤素气体和含碳气体。 气体混合物的含氮气体的体积浓度在约20％至约30％的范围内。 气体混合物中含碳气体与含卤素气体的体积浓度比等于约0.3。 该方法还包括通过硬掩模层中的开口蚀刻介电层，以形成电介质层中的特征开口。 该方法包括在特征开口中形成导电材料。