公开(公告)号：US20150311175A1

公开(公告)日：2015-10-29

申请号：US14697235

申请日：2015-04-27

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chih-Wei HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/49811 ,  B81B7/007 ,  B81B2207/093 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/06165 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/4801 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81469 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/19107 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.

Abstract translation: 提供堆叠的芯片封装。 堆叠的芯片封装包括具有第一侧和与其相对的第二侧的第一基板。 第一基板在其中包括凹部。 所述凹部邻接所述第一基板的侧边缘。 多个再分配层设置在第一基板上并延伸到凹部的底部。 第二基板设置在第一基板的第一侧上。 多个接合线相应地设置在凹部中的再分配层上并且延伸到第二基板上。 器件衬底设置在第一衬底的第二侧上。 还提供了形成堆叠芯片封装的方法。

公开(公告)号：US20130341747A1

公开(公告)日：2013-12-26

申请号：US13921999

申请日：2013-06-19

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

IPC: H01L31/0232 ,  H01L31/02

CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。

公开(公告)号：US20130307137A1

公开(公告)日：2013-11-21

申请号：US13898300

申请日：2013-05-20

Applicant: XINTEC INC.

Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Yu-Min LIANG

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L23/498 ,  B81B7/0077 ,  H01L21/78 ,  H01L24/94 ,  H01L27/14618 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.

Abstract translation: 本发明的实施例提供了一种芯片封装，包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述第一表面上的电介质层; 以及导电焊盘结构，其设置在所述电介质层中并电连接到所述器件区域; 设置在所述芯片和所述盖基板之间的覆盖基板，其中所述间隔层，空腔由所述芯片和所述器件区域上的覆盖基板所围绕，并且所述间隔层与所述芯片直接接触而没有任何粘合胶 设置在芯片和间隔层之间。

公开(公告)号：US20160329283A1

公开(公告)日：2016-11-10

申请号：US15140289

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Yu-Tung CHEN ,  Chien-Min LIN ,  Chuan-Jin SHIU ,  Chih-Wei HO ,  Yen-Shih HO

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L21/027 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

Abstract translation: 半导体结构包括第一基板，第二基板，阻挡层，光致抗蚀剂层和导电层。 第一基板具有导电垫。 第二基板具有通孔，围绕通孔的侧壁表面，第一表面和与第一表面相对的第二表面。 通孔穿过第一和第二表面。 导电垫与通孔对齐。 坝层位于第一基板和第二表面之间。 坝层朝向通孔突出。 光致抗蚀剂层位于第一表面上，侧壁表面，阻挡层朝向通孔突出，并且在导电垫和阻挡层之间朝向通孔突出。 导电层位于光致抗蚀剂层和导电垫上。

公开(公告)号：US20150099357A1

公开(公告)日：2015-04-09

申请号：US14508989

申请日：2014-10-07

Applicant: XINTEC INC.

Inventor： Chuan-Jin SHIU ,  Tsang-Yu LIU ,  Chih-Wei HO ,  Shih-Hsing CHAN ,  Ching-Jui CHUANG

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L21/32139 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/11821 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/0105 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

Abstract translation: 提供了制造晶片级芯片封装的方法。 首先，提供具有两个相邻芯片的晶片，所述晶片具有上表面和下表面，并且每个芯片的一侧在下表面上包括导电焊盘。 凹部和隔离层从上表面延伸到下表面，凹部暴露导电垫。 隔离层的一部分设置在具有开口的凹部中以暴露导电垫。 在隔离层和导电焊盘上形成导电层，并且将光致抗蚀剂层喷涂在导电层上。 曝光和显影光致抗蚀剂层以暴露导电层，并且蚀刻导电层以形成再分布层。 在剥离光刻胶层之后，在隔离层和再分布层上形成焊料层。