公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US11873212B2

公开(公告)日：2024-01-16

申请号：US17184443

申请日：2021-02-24

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20160240520A1

公开(公告)日：2016-08-18

申请号：US15007124

申请日：2016-01-26

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen

IPC: H01L25/16 ,  H01L21/304 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract translation: 芯片封装包括芯片，电介质结合层，载体和再分配层。 芯片具有基板，导电焊盘和保护层。 电介质接合层位于保护层上，载体和保护层之间。 载体，介电接合层和保护层具有被配置为暴露导电垫的连通通孔。 再分配层包括连接部分和无源部件部分。 连接部分位于导电垫上，通孔的侧壁和载体的表面背离电介质结合层。 无源部件位于载体的表面上，无源部件的一端与载体表面上的连接部分连接。

公开(公告)号：US09972584B2

公开(公告)日：2018-05-15

申请号：US15140199

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Hsing-Lung Shen ,  Jiun-Yen Lai ,  Yu-Ting Huang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31 ,  H01L31/0203 ,  H01L21/78 ,  H01L31/0216 ,  H01L33/62 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/32 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/62 ,  H01L2224/11

Abstract: A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.

公开(公告)号：US09548265B2

公开(公告)日：2017-01-17

申请号：US15138119

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen ,  Yu-Hao Su ,  Kuan-Jung Wu ,  Yi Cheng

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L21/687 ,  H01L49/02

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract translation: 芯片封装包括芯片，隔离层和再分配层。 芯片具有基板，电焊盘和保护层。 基板具有第一表面和第二表面。 基板具有通孔，保护层具有凹孔，使得电焊盘通过凹孔和通孔露出。 隔离层位于第二表面，通孔的侧壁和凹孔的侧壁上。 再分配层包括连接部分和无源元件部分。 连接部分位于隔离层上并与电焊垫电接触。 无源元件部分位于第二表面上的隔离层上，无源元件部分的一端连接到第二表面上的连接部分。

公开(公告)号：US11137559B2

公开(公告)日：2021-10-05

申请号：US16851099

申请日：2020-04-17

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Yu-Ting Huang ,  Hsing-Lung Shen ,  Tsang-Yu Liu ,  Hui-Hsien Wu

IPC: G02B6/42

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

公开(公告)号：US11107759B2

公开(公告)日：2021-08-31

申请号：US17037151

申请日：2020-09-29

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC: H01L23/498 ,  H01L21/48

Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.

公开(公告)号：US09793234B2

公开(公告)日：2017-10-17

申请号：US15091122

申请日：2016-04-05

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/4846 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/08267 ,  H01L2224/08268 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16267 ,  H01L2224/16268 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.