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    IMAGE SENSOR CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    1.
    发明申请
    IMAGE SENSOR CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    图像传感器芯片封装及其形成方法

    公开(公告)号：US20120049307A1

    公开(公告)日：2012-03-01

    申请号：US13217999

    申请日：2011-08-25

    申请人： Yu-Lung HUANG ,  Tzu-Hsiang HUNG ,  Yen-Shih HO

    发明人： Yu-Lung HUANG ,  Tzu-Hsiang HUNG ,  Yen-Shih HO

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L31/1876 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/13 ,  H01L2224/94

    摘要： A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.

    摘要翻译： 一种用于形成图像传感器芯片封装的方法，包括：提供具有限定在其上的预定划线的基板，其中，所述预定划线限定器件区域，并且每个器件区域至少具有形成在其中的器件; 将支撑基板设置在所述基板的第一表面上; 在所述支撑基板和所述基板之间形成至少间隔层，其中所述间隔层覆盖所述预定划线; 在所述基板的第二表面上形成封装层; 在所述衬底的第二表面上形成导电结构，其中所述导电结构分别在相应的一个所述器件区域中电连接到相应的器件; 并且沿着预定的划线切割，使得支撑基板从基板移除，并且基板被分离成多个单独的图像传感器芯片封装。

    CHIP PACKAGE
    2.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20120056226A1

    公开(公告)日：2012-03-08

    申请号：US13224267

    申请日：2011-09-01

    申请人： Tzu-Hsiang HUNG ,  Hsin-Chih CHIU ,  Chuan-Jin SHIU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Yu-Min LIANG

    发明人： Tzu-Hsiang HUNG ,  Hsin-Chih CHIU ,  Chuan-Jin SHIU ,  Chia-Sheng LIN ,  Yen-Shih HO ,  Yu-Min LIANG

    IPC分类号： H01L33/58 ,  H01L31/0232

    CPC分类号： H01L27/14618 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

    INTERPOSER AND METHOD FOR FORMING THE SAME
    4.
    发明申请
    INTERPOSER AND METHOD FOR FORMING THE SAME 有权
    插入物及其形成方法

    公开(公告)号：US20120193811A1

    公开(公告)日：2012-08-02

    申请号：US13360435

    申请日：2012-01-27

    申请人： Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    发明人： Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC分类号： H01L23/498 ,  H01L21/768

    CPC分类号： H01L23/492 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K2201/10378 ,  H01L2924/00

    摘要： An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

    摘要翻译： 本发明的实施例提供一种插入器，其包括：具有第一表面和第二表面的基板; 从所述第一表面朝向所述第二表面延伸的第一孔; 从所述第一表面朝向所述第二表面延伸的第二孔，其中所述第一孔的宽度与所述第二孔的宽度不同; 位于所述基板上并延伸到所述第一孔的侧壁和所述第二孔的侧壁上的绝缘层; 以及导电层，其位于所述基板上的所述绝缘层上并且延伸到所述第一孔的侧壁上，其中在所述第二孔中基本上没有导电层。

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20120146111A1

    公开(公告)日：2012-06-14

    申请号：US13324815

    申请日：2011-12-13

    申请人： Shu-Ming CHANG ,  Yen-Shih HO ,  Ho-Yin YIU

    发明人： Shu-Ming CHANG ,  Yen-Shih HO ,  Ho-Yin YIU

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/76898 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/157 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package including a semiconductor substrate, a drain electrode, a source electrode and a gate electrode. The semiconductor substrate has a first surface and an opposite second surface wherein the second surface has a recess. The drain electrode is disposed on the first surface and covers the recess. The source electrode is disposed on the second surface in a position corresponding to the drain electrode covering the recess. The gate electrode is disposed on the second surface. An embodiment of the invention further provides a manufacturing method of a chip package.

    摘要翻译： 本发明的实施例提供一种包括半导体衬底，漏电极，源电极和栅电极的芯片封装。 半导体衬底具有第一表面和相对的第二表面，其中第二表面具有凹部。 漏电极设置在第一表面上并覆盖凹部。 源电极设置在与覆盖凹部的漏电极对应的位置的第二表面上。 栅电极设置在第二表面上。 本发明的实施例还提供了一种芯片封装的制造方法。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    8.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20120319297A1

    公开(公告)日：2012-12-20

    申请号：US13524985

    申请日：2012-06-15

    申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

    发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC分类号： H01L23/48 ,  H01L21/78

    CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

    摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。