公开(公告)号：US09324911B2

公开(公告)日：2016-04-26

申请号：US13720284

申请日：2012-12-19

Applicant: Soitec

Inventor： Chantal Arena ,  Robin Scott ,  Claudio Canizares

IPC: H01L33/32 ,  H01L21/02 ,  H01L31/0687 ,  H01L27/15 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/323 ,  H01L33/00 ,  H01L33/08

CPC classification number: H01L33/32 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02664 ,  H01L27/153 ,  H01L31/03048 ,  H01L31/0687 ,  H01L31/1848 ,  H01L33/0062 ,  H01L33/08 ,  H01S5/32341 ,  H01S5/32358 ,  Y02E10/544

Abstract: Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride material into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a hydride vapor phase epitaxy (HVPE) chamber.

Abstract translation: 稀氮化物III-V半导体材料可以通过用先前形成的氮化物材料中的一些N原子取代As原子将至少一部分先前形成的氮化物材料转化成包括砷的稀氮化物III-V半导体材料来形成。 这种方法可以用于制造光电器件，例如光伏电池和光电放电器。 该方法可以在沉积室内进行，例如金属有机化学气相沉积（MOCVD）或氢化物气相外延（HVPE）室。

公开(公告)号：US09293473B2

公开(公告)日：2016-03-22

申请号：US14612772

申请日：2015-02-03

Applicant: Soitec

Inventor： Patrick Reynaud ,  Sebastien Kerdiles ,  Daniel Delprat

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

公开(公告)号：US09293448B2

公开(公告)日：2016-03-22

申请号：US14474503

申请日：2014-09-02

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka

IPC: G02B6/12 ,  H01L25/16 ,  H01L31/103 ,  H01L27/06 ,  H01L27/12 ,  H01L33/34

CPC classification number: H01L25/167 ,  G02B6/12002 ,  G02B6/12004 ,  H01L27/0688 ,  H01L27/1203 ,  H01L31/103 ,  H01L33/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Abstract translation: 三维集成半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。 光学互连可操作地耦合到光活性器件。 半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。 形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。 可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。 半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

公开(公告)号：US09275893B2

公开(公告)日：2016-03-01

申请号：US14426509

申请日：2013-04-10

Applicant: Soitec

Inventor： Alexandre Barthelemy

IPC: H01L21/762

CPC classification number: H01L21/76259 ,  H01L21/76254

Abstract: The present disclosure concerns a method of detaching a layer to be detached from a donor substrate, comprising the following steps: a) assembling the donor substrate and a porous substrate, b) application of a treatment of chemical modification of the crystallites, the chemical modification being adapted to generate a variation of the volume of the crystallites, the volume variation generates deformation in compression or in tension of the porous substrate, the deformation in compression or in tension generates a stress in tension or in compression in the donor substrate, which causes fracture in a fracture plane, the fracture plane delimiting the layer to be detached, the stress leading to the detachment of the layer to be detached from the donor substrate.

Abstract translation: 本公开涉及一种从施主衬底分离待分离的层的方法，包括以下步骤：a）组合施主衬底和多孔衬底，b）施加微晶化学改性的处理，化学改性 适于产生微晶体积的变化，体积变化在多孔基材的压缩或张力中产生变形，压缩或拉伸中的变形在供体基底中产生张力或压缩中的应力，这导致 在断裂平面中断裂，限定要分离的层的断裂面，导致从供体基底脱离的层的应力。

公开(公告)号：US20160056318A1

公开(公告)日：2016-02-25

申请号：US14780473

申请日：2014-03-26

Applicant: SOITEC ,  FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

Inventor： Cecile Aulnette ,  Rainer Krause ,  Frank Dimroth ,  Matthias Grave ,  Eric Guiot ,  Eric Mazaleyrat ,  Charlotte Drazek

IPC: H01L31/0443 ,  H01L31/028 ,  H01L31/0693 ,  H01L31/054 ,  H01L31/0687

CPC classification number: H01L31/0443 ,  H01L27/1421 ,  H01L31/052 ,  H01L31/0687 ,  Y02E10/52 ,  Y02E10/544 ,  Y02P70/521

Abstract: This disclosure relates to a solar cell assembly structure for supporting a concentrator photovoltaic cell structure (3420), comprising a semiconducting structure and a diode, wherein the semiconducting structure comprises a first semiconducting region at least a part of which for placing the concentrator photovoltaic cell structure, and a second semiconducting region for realizing the diode within or on the second semiconducting region and wherein the part of the first semiconducting region for placing the concentrator photovoltaic cell structure and the second semiconducting region are not vertically overlapping.

Abstract translation: 本公开涉及一种用于支撑聚光器光伏电池结构（3420）的太阳能电池组件结构，其包括半导体结构和二极管，其中所述半导体结构包括第一半导体区域，其至少一部分用于将集中器光伏电池结构 以及用于在第二半导体区域内或其上实现二极管的第二半导体区域，并且其中用于放置集中器光伏电池结构和第二半导体区域的第一半导体区域的部分不是垂直重叠的。

公开(公告)号：US20160042989A1

公开(公告)日：2016-02-11

申请号：US14780467

申请日：2014-03-21

Applicant: SOITEC

Inventor： Sebastien Kerdiles ,  Guillaume Chabanne ,  Francois Boedt

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/12 ,  H01L29/0649

Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

Abstract translation: 本公开涉及一种用于制造复合结构的方法，该方法包括以下步骤：a）提供施主衬底和载体衬底; b）形成电介质层; c）形成覆盖层; d）在供体衬底中形成弱化区; e）通过具有轮廓的接触表面接合载体基底和施主基底; f）通过弱化区域破坏施主衬底，执行步骤b）和e），使得轮廓被刻划在轮廓中，并且步骤c）被执行以使覆盖层覆盖电介质层的周边表面。

公开(公告)号：US09246057B2

公开(公告)日：2016-01-26

申请号：US14211590

申请日：2014-03-14

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/04 ,  H01L33/16

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个包含InwGa1-wN的阱层和至少一个包含接近至少一个阱层的InbGa1-bN的势垒层。 在一些实施例中，阱层的InwGa1-wN中的w的值在一些实施例中可以大于或等于约0.10且小于或等于约0.40，并且在InbGa1-bN中的b的值在 至少一个阻挡层可以大于或等于约0.01且小于或等于约0.10。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US09219150B1

公开(公告)日：2015-12-22

申请号：US14489817

申请日：2014-09-18

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L23/52 ,  H01L21/8238 ,  H01L21/30 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/306 ,  H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract translation: 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US20150364364A1

公开(公告)日：2015-12-17

申请号：US14377738

申请日：2013-01-28

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Oleg Kononchuk ,  Ionut Radu

IPC: H01L21/762 ,  B32B7/04 ,  B32B9/04

CPC classification number: H01L21/76254 ,  B32B7/04 ,  B32B9/04 ,  B32B2457/14 ,  Y10T428/24802

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract translation: 一种包括以下步骤的方法：提供支撑衬底和供体衬底，在所述供体衬底中形成脆化区域，以限定所述脆化区域的任一侧上的第一部分和第二部分，将所述施主衬底组装在所述支撑体上 底物，沿着脆化破坏施主衬底。 此外，该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。

公开(公告)号：US20150340430A1

公开(公告)日：2015-11-26

申请号：US14817464

申请日：2015-08-04

Applicant: Soitec

Inventor： Christiaan J. Werkhoven ,  Chantal Arena

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/26 ,  H01L29/20

CPC classification number: H01L21/2654 ,  H01L21/0242 ,  H01L21/02425 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02634 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/6835 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/0079 ,  H01L33/647 ,  H01L2221/68318 ,  H01L2221/68363

Abstract: Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments.

Abstract translation: 实施例涉及形成半导体结构的半导体结构和方法。 半导体结构包括具有与在衬底层上形成的一层或多层半导体材料的CTE紧密匹配的CTE的衬底层。 在一些实施例中，衬底层可以包括包括两个或更多个元件的复合衬底材料。 在一些实施例中，基底层可以包括金属材料和/或陶瓷材料。