公开(公告)号：US20070246802A1

公开(公告)日：2007-10-25

申请号：US11702624

申请日：2007-02-06

申请人： Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

发明人： Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/02609 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/02532

摘要： A semiconductor device and method thereof. The example method may include forming a semiconductor device, including forming a first layer on a substrate, the first layer including aluminum nitride (AlN), forming a second layer by oxidizing a surface of the first layer and forming a third layer on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes. The example semiconductor device may include a substrate including a first layer, the first layer including aluminum nitride (AlN), a second layer formed by oxidizing a surface of the first layer and a third layer formed on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes.

摘要翻译： 半导体器件及其方法。 示例性方法可以包括形成半导体器件，包括在衬底上形成第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面并在第二层上形成第三层来形成第二层 ，第一层，第二层和第三层各自相对于多个晶面之一高度取向。 示例性半导体器件可以包括：衬底，其包括第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面形成的第二层和形成在第二层上的第三层，第一层，第二层和第二层 第三层各自相对于多个晶面之一高度取向。

公开(公告)号：US20060144323A1

公开(公告)日：2006-07-06

申请号：US11311228

申请日：2005-12-20

申请人： Wenxu Xianyu ,  Takashi Noguchi ,  Young-soo Park ,  Hans Cho ,  Huaxiang Yin

发明人： Wenxu Xianyu ,  Takashi Noguchi ,  Young-soo Park ,  Hans Cho ,  Huaxiang Yin

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/26506 ,  H01L21/268 ,  H01L21/32134 ,  H01L21/76254 ,  H01L21/76256 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/66772

摘要： A method of fabricating a large substrate with a locally integrated single crystalline silicon layer is provided. The method includes: forming a buffer layer on a support plate; separately fabricating a single crystalline silicon layer; attaching the single crystalline silicon layer having a predetermined thickness, which is separately fabricated, to a predetermined portion in the support plate; forming a non-single crystalline silicon layer having a predetermined thickness to cover the single crystalline silicon layer and the buffer layer; and processing the non-single crystalline silicon layer to expose a surface of the non-single crystalline silicon layer and to level the surface of the non-single crystalline silicon layer with a surface of the amorphous silicon layer.

公开(公告)号：US20060134894A1

公开(公告)日：2006-06-22

申请号：US11283874

申请日：2005-11-22

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

IPC分类号： H01L21/84 ,  H01L21/20

CPC分类号： H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L27/1281

摘要： A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

摘要翻译： 提供一种制造多晶Si膜的方法和制造堆叠晶体管的方法。 制造多晶Si膜的方法包括制备绝缘基板，其上形成有依次形成的多晶硅，具有多晶硅有源层，栅极绝缘层和栅极，形成与栅极分离的互连金属线， 形成覆盖晶体管和互连金属线的绝缘层，在绝缘层上形成非晶硅层; 并退火非晶硅层。

公开(公告)号：US20060068507A1

公开(公告)日：2006-03-30

申请号：US11233363

申请日：2005-09-23

申请人： Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Jang-Yeon Kwon ,  Huaxiang Yin

发明人： Wenxu Xianyu ,  Takashi Noguchi ,  Hans Cho ,  Jang-Yeon Kwon ,  Huaxiang Yin

IPC分类号： H01L21/00 ,  H01L21/8242

CPC分类号： H01L21/02356 ,  H01L21/02197 ,  H01L21/31691 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/12

摘要： A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric film includes preparing a substrate, depositing an amorphous ferroelectric film on the substrate, and crystallizing the amorphous ferroelectric film by irradiating it with a laser beam. According to still another example embodiment of the present invention, a method of forming a ferroelectric film may reduce the thermal damage to other elements because the ferroelectric film may be formed at a temperature lower than about 500° C. to about 550°C.

摘要翻译： 提供了形成材料（例如铁电体）膜的方法，制造电容器的方法，以及使用形成（例如铁电体）膜的方法形成半导体存储器件的方法。 根据本发明的示例性实施例，形成铁电体膜的方法包括制备基板，在基板上沉积非晶铁电体膜，并通过用激光束照射非晶强电介质膜使其结晶。 根据本发明的另一示例性实施例，形成铁电体膜的方法可以减少对其它元件的热损伤，因为铁电体膜可以在低于约500℃至约550℃的温度下形成。

公开(公告)号：US20050145843A1

公开(公告)日：2005-07-07

申请号：US11013398

申请日：2004-12-17

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7855

摘要： A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.

摘要翻译： 提供薄膜晶体管及其制造方法。 薄膜晶体管包括基板; 形成在所述基板上的缓冲层; 在缓冲层上彼此间隔开的源极和漏极; 形成在所述缓冲层上的沟道层，以将所述源极和所述漏极彼此连接; 以及形成在缓冲层上以与源极，漏极和沟道层间隔开的栅极。

公开(公告)号：US09054018B2

公开(公告)日：2015-06-09

申请号：US13812503

申请日：2012-10-12

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC分类号： H01L29/06 ,  H01L21/84 ,  H01L29/15 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/51 ,  H01L29/165

CPC分类号： H01L29/15 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/151 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/7781 ,  H01L29/785 ,  H01L29/7853

摘要： The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

摘要翻译： 本发明公开了一种半导体器件的制造方法，其特征在于，在基板上形成沿着第一方向延伸并具有菱形状的横截面的多个翅片， 在每个翅片上形成栅极堆叠结构，其横过所述多个翅片并沿着第二方向延伸; 其中位于所述栅极堆叠结构下方的每个鳍中的部分形成所述器件的沟道区，并且沿着所述第一方向位于所述栅极堆叠结构两侧的每个鳍中的部分形成源极和漏极区。 根据本发明的半导体器件及其制造方法使用菱形翅片来提高栅极控制能力以有效地抑制短沟道效应，此外，在其中使用外延量子阱以更好地限制载流子，从而改善器件 驱动能力。

公开(公告)号：US20140217519A1

公开(公告)日：2014-08-07

申请号：US13989297

申请日：2012-07-30

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and epitaxially growing an LDD material layer to form LDD regions of the device.

摘要翻译： 公开了一种包括外延LDD和Halo区域的晶体管器件及其制造方法。 根据本公开的实施例，该方法可以包括：在半导体衬底上形成栅极堆叠; 形成覆盖栅极堆叠的顶部和栅极叠层的侧壁的栅极间隔物; 形成源极/漏极沟槽; 在源极/漏极沟槽中外延生长Halo材料层，其中Halo材料层在其中具有第一掺杂元素; 外延生长的源极/漏极区域，其对器件的沟道区域施加应力，其中源极/漏极区域具有与第一掺杂元件的导电性相反的第二掺杂元素; 各向同性蚀刻源/漏区以去除源极/漏极区的部分，其中蚀刻还将栅极间隔物正下方的Halo材料层的部分去除并在一定程度上延伸到沟道区，其中Halo材料的剩余部分 层构成设备的光晕区域; 并外延生长LDD材料层以形成器件的LDD区域。

公开(公告)号：US20140057418A1

公开(公告)日：2014-02-27

申请号：US13812502

申请日：2012-10-12

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC分类号： H01L21/02 ,  H01L29/12

CPC分类号： H01L21/0257 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/12

摘要： The present invention discloses a method for manufacturing a high mobility material layer, comprising: forming a plurality of precursors in/on a substrate; and performing a pulse laser processing such that the plurality of precursors react with each other to produce a high mobility material layer. Furthermore, the present invention also provides a method for manufacturing a semiconductor device, comprising: forming a buffer layer on an insulating substrate; forming a first high mobility material layer on the buffer layer using the method for manufacturing the high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the method for manufacturing the high mobility material layer; and forming trench isolations and defining active regions in the first and second high mobility material layers.

摘要翻译： 本发明公开了一种高迁移率材料层的制造方法，其特征在于，包括：在基板内/内形成多个前体; 并进行脉冲激光处理使得多个前体彼此反应以产生高迁移率材料层。 此外，本发明还提供一种半导体器件的制造方法，包括：在绝缘基板上形成缓冲层; 使用高迁移率材料层的制造方法在缓冲层上形成第一高迁移率材料层; 使用所述高迁移率材料层的制造方法在所述第一高迁移率材料层上形成第二高迁移率材料层; 以及形成沟槽隔离并在第一和第二高迁移率材料层中限定有源区。

公开(公告)号：US20130316509A1

公开(公告)日：2013-11-28

申请号：US13580962

申请日：2012-06-12

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

摘要翻译： 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法，其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅，以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散，从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量，因此如果在源极/漏极区域的外延生长之前执行HALO，则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO，则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

公开(公告)号：US20130256664A1

公开(公告)日：2013-10-03

申请号：US13519884

申请日：2012-04-10

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/10 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

摘要翻译： 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。