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    Magnetic state element and circuits
    92.
    发明授权
    Magnetic state element and circuits 有权
    磁状态元件和电路

    公开(公告)号：US09570139B2

    公开(公告)日：2017-02-14

    申请号：US14696965

    申请日：2015-04-27

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

    IPC: G11C11/00 ,  G11C11/16 ,  H03K19/16

    CPC classification number: H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

    Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

    Abstract translation: 描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。 描述的磁解除多路复用器包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。

    NON-VOLATILE REGISTER FILE INCLUDING MEMORY CELLS HAVING CONDUCTIVE OXIDE MEMORY ELEMENT
    93.
    发明申请
    NON-VOLATILE REGISTER FILE INCLUDING MEMORY CELLS HAVING CONDUCTIVE OXIDE MEMORY ELEMENT 审中-公开
    非易失性寄存器文件，包括具有导电氧化物存储元件的存储器单元

    公开(公告)号：US20160141031A1

    公开(公告)日：2016-05-19

    申请号：US14546061

    申请日：2014-11-18

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

    IPC: G11C16/04 ,  G11C14/00 ,  G06F12/02

    CPC classification number: H01L45/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C13/0007 ,  G11C13/0026 ,  G11C14/0018 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

    Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

    Abstract translation: 一些实施例包括具有包括在非易失性存储单元中的存储元件，晶体管，耦合到晶体管的栅极的接入线，第一导线和第二导线的装置和方法。 存储元件可以包括位于衬底之上且位于第一和第二导电线之间的导电氧化物材料。 存储元件包括耦合到晶体管的漏极的一部分和耦合到第二导线的另一部分。 第一导线被耦合到晶体管的源极并且可以位于存取线和存储元件之间。 进入线具有在第一方向上延伸的长度并且可以位于基板和存储元件之间。 第一和第二导线具有沿第二方向延伸的长度。

    In-memory analog neural cache
    100.
    发明授权
    In-memory analog neural cache 有权

    公开(公告)号：US11502696B2

    公开(公告)日：2022-11-15

    申请号：US16160800

    申请日：2018-10-15

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC: H03M1/00 ,  H03M1/12 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

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