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222 条记录 (耗时 0.033 秒)

    CMOS BACK-GATED KEEPER TECHNIQUE
    95.
    发明申请
    CMOS BACK-GATED KEEPER TECHNIQUE 失效

    公开(公告)号：US20090224803A1

    公开(公告)日：2009-09-10

    申请号：US12045500

    申请日：2008-03-10

    申请人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Andres Bryant ,  Wilfried Haensch

    IPC分类号： H03K19/20

    CPC分类号： H03K19/0008 ,  H03K3/356104 ,  H03K2217/0018

    摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

    MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL
    97.
    发明申请
    MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL 审中-公开
    多个水平多端口注册文件

    公开(公告)号：US20080291767A1

    公开(公告)日：2008-11-27

    申请号：US11751315

    申请日：2007-05-21

    申请人： Joseph S. Barnes ,  Jagreet S. Atwal ,  Kerry Bernstein ,  Robert J. Bucki

    发明人： Joseph S. Barnes ,  Jagreet S. Atwal ,  Kerry Bernstein ,  Robert J. Bucki

    IPC分类号： G11C8/00 ,  H01L21/4763

    CPC分类号： H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203

    摘要： A multi-port register file (e.g., memory element) is provided in which each read port of the register file is located in a separate wafer above and/or below the primary data storage element. This is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stacked and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stacked layer.

    摘要翻译： 提供多端口寄存器文件（例如，存储器元件），其中寄存器堆的每个读端口位于主数据存储元件上方和/或下方的单独晶片中。 这在本发明中通过利用三维积分来实现，其中多个有源电路层被垂直堆叠并且使用垂直排列的互连将装置从堆叠层之一连接到另一层叠层中的另一装置。

    DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR
    98.
    发明申请
    DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
    根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态

    公开(公告)号：US20080285338A1

    公开(公告)日：2008-11-20

    申请号：US12180776

    申请日：2008-07-28

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C11/34

    CPC分类号： G11C11/417

    摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

    摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

    SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
    100.
    发明申请
    SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT 有权
    用于设计低漏电单声道CMOS逻辑电路的系统和方法

    公开(公告)号：US20080195987A1

    公开(公告)日：2008-08-14

    申请号：US12103038

    申请日：2008-04-15

    申请人： Kerry Bernstein ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Norman J. Rohrer

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

    摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.

    摘要翻译： 一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。 执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。