公开(公告)号：US08837212B2

公开(公告)日：2014-09-16

申请号：US14038472

申请日：2013-09-26

Applicant: Micron Technology, Inc.

Inventor： Roy E. Meade ,  Gurtej S. Sandhu

IPC: G11C11/14 ,  H05K3/36 ,  H05K1/14 ,  H01L23/00 ,  H05K7/04 ,  G11C11/16 ,  H05K1/11 ,  B82Y99/00 ,  H05K3/34

CPC classification number: H05K1/0298 ,  B82Y99/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C19/0808 ,  H01L24/02 ,  H01L24/80 ,  H01L2224/04042 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/112 ,  H05K1/113 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/36 ,  H05K3/4697 ,  H05K7/04 ,  H05K2201/09381 ,  Y10S977/932 ,  Y10T29/49126 ,  Y10T29/49128 ,  H01L2924/00

Abstract: Electronic devices may include a first substrate bearing circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. A second substrate may be electrically connected to at least one of the microscale bond pads. Methods of forming electronic devices may include positioning a first substrate adjacent to a second substrate. The first substrate may bear circuitry components at a nanoscale pitch within the first substrate. The first substrate may include microscale bond pads on a surface of the first substrate. A via may electrically connect one of the microscale bond pads to one of the circuitry components. The second substrate may be electrically connected to at least one of the microscale bond pads.

Abstract translation: 电子器件可以包括第一衬底，其承载在第一衬底内的纳米级间距的电路组件。 第一衬底可以包括在第一衬底的表面上的微结构焊盘。 通孔可以将微型接合焊盘之一电连接到电路部件之一。 第二衬底可以电连接到至少一个微结构焊盘。 形成电子器件的方法可以包括将邻近第二衬底的第一衬底定位。 第一衬底可以承载第一衬底内的纳米级间距的电路组件。 第一衬底可以包括在第一衬底的表面上的微结构焊盘。 通孔可以将微型接合焊盘之一电连接到电路部件之一。 第二衬底可以电连接到至少一个微结构焊盘。

公开(公告)号：US20140252301A1

公开(公告)日：2014-09-11

申请号：US14253989

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/52 ,  G11C2213/53 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state.

Abstract translation: 本文描述了开关器件结构和方法。 切换装置可以包括垂直堆叠，其包括形成在第一和第二电极之间的材料。 开关装置还可以包括耦合到垂直堆叠的第三电极，并且被配置为接收施加到其上的电压以控制第一和第二电极之间的材料中的导电路径的形成状态，其中导电路径的形成状态 可以在接通状态和断开状态之间切换。

公开(公告)号：US08804414B2

公开(公告)日：2014-08-12

申请号：US13926780

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Steven J. Kramer ,  Gurtej S. Sandhu

IPC: G11C11/15

CPC classification number: G11C11/161 ,  G11C11/1675 ,  G11C11/22 ,  G11C11/5607 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括位于铁磁存储材料和与反铁磁材料接触的被钉扎铁磁材料之间的隧道阻挡材料。 隧道阻挡材料是多铁性材料，反铁磁材料，铁磁存储材料和钉扎铁磁材料位于第一电极和第二电极之间。

公开(公告)号：US20140203409A1

公开(公告)日：2014-07-24

申请号：US14221655

申请日：2014-03-21

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kristina K. Parat

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L21/76254 ,  H01L21/78 ,  H01L21/8221 ,  H01L23/3185 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

Abstract translation: 公开了在没有电路的受主基板上制造集成电路器件的方法。 集成电路器件通过在接受器衬底上依次布置一个或多个半导体材料层并且在配置下一较高电平之前在每个级别的半导体材料上制造电路而形成。 在封装电路之后，去除受主衬底并切割半导体晶片。 还公开了通过这些方法形成的集成电路器件。

公开(公告)号：US20140009991A1

公开(公告)日：2014-01-09

申请号：US13972455

申请日：2013-08-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gurtej S. Sandhu

IPC: G11C13/00

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US20130323895A1

公开(公告)日：2013-12-05

申请号：US13959455

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  D. Mark Durcan

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  Y10S438/962

Abstract: Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nano scale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nano scale structures. According to various embodiments, the nano scale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Abstract translation: 可以使用在半导体衬底上生长纳米尺度结构的方法来制造器件。 根据各种实施方案，可以在基材的表面上形成成核位点。 成核位点的产生可以包括用选择的能量和剂量植入离子，以提供成核位点跨越衬底的表面的可控分布。 可以使用成核位点的可控分布来生长纳米尺度结构以使纳米尺度结构的生长生长。 根据各种实施方案，纳米级结构可以包括纳米晶体，纳米线或纳米管中的至少一种。 根据各种纳米晶体实施例，纳米晶体可以位于栅极堆叠内，并且用作非易失性器件的浮动栅极。 本文提供了其他实施例。

公开(公告)号：US20130292628A1

公开(公告)日：2013-11-07

申请号：US13903307

申请日：2013-05-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1683

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.

Abstract translation: 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。 形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成亚化学计量氧化物，在亚化学计量氧化物上形成第二导电元件，以及通过使亚化学计量氧化物氧化成氧化环境来氧化亚化学计量氧化物的边缘 以限定氧化物中心附近的受控氧空位传导路径。

公开(公告)号：US20130286727A1

公开(公告)日：2013-10-31

申请号：US13926397

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/16 ,  H01L43/02

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括在第一铁磁材料和第二铁磁材料之间包括非磁性材料的环形STT堆叠和围绕环形STT堆叠的至少一部分的软磁材料。

公开(公告)号：US20130286722A1

公开(公告)日：2013-10-31

申请号：US13926780

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Stephen J. Kramer ,  Gurtej S. Sandhu

IPC: G11C11/16 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1675 ,  G11C11/22 ,  G11C11/5607 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material. The tunneling barrier material is a multiferroic material and the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are positioned between a first electrode and a second electrode.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括位于铁磁存储材料和与反铁磁材料接触的被钉扎铁磁材料之间的隧道阻挡材料。 隧道阻挡材料是多铁性材料，反铁磁材料，铁磁存储材料和钉扎铁磁材料位于第一电极和第二电极之间。

公开(公告)号：US20130273690A1

公开(公告)日：2013-10-17

申请号：US13915373

申请日：2013-06-11

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

Abstract: Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure.

Abstract translation: 存储器件和形成方法包括位于第一电极和第二电极之间的混合的价氧化物。 在电极之一的表面下方植入金属，可以形成与电极直接界面的混合的价氧化物。 可以通过退火该结构，在混合的价氧化物和电极之间形成金属间氧化物。