公开(公告)号：US07721970B2

公开(公告)日：2010-05-25

申请号：US11309044

申请日：2006-06-13

Applicant: Chun-Chi Liang ,  Hsuan-Tsung Chen ,  Yu Huang

Inventor： Chun-Chi Liang ,  Hsuan-Tsung Chen ,  Yu Huang

IPC: G06K13/04

CPC classification number: G06K7/0013 ,  G06F1/187 ,  G07F19/205

Abstract: A mounting apparatus for mounting a card reader that defines a fixing hole in a sidewall thereof, and forms a first connector in a rear wall thereof, includes a chassis, a bracket slidably mounted to the chassis, a pair of first resilient members, and a locking member. The chassis includes a front wall defining a first opening for the card reader passing therethrough. A second connector is mounted to the bracket, corresponding to the first connector of the card reader. The first resilient members are connected between the chassis and the bracket. The first resilient members are stretched when mounting the card reader. The locking member includes a retaining member mounted to the chassis, and a securing member mounted to the retaining member via a second resilient member. The securing member includes a securing portion protruding therefrom for engaging with the fixing hole of the card reader.

Abstract translation: 一种用于安装在其侧壁中形成固定孔并且在其后壁中形成第一连接器的读卡器的安装装置，包括底架，可滑动地安装到底架的托架，一对第一弹性构件和 锁定构件。 底盘包括限定用于读卡器通过的第一开口的前壁。 第二连接器安装到支架上，对应于读卡器的第一连接器。 第一弹性构件连接在底盘和支架之间。 安装读卡器时，第一弹性构件被拉伸。 锁定构件包括安装到底盘的保持构件和经由第二弹性构件安装到保持构件的固定构件。 固定构件包括从其突出的固定部分，用于与读卡器的固定孔接合。

公开(公告)号：US20100093158A1

公开(公告)日：2010-04-15

申请号：US11543353

申请日：2006-10-04

Applicant: Charles M. Lieber ,  Yi Cui ,  Xiangfeng Duan ,  Yu Huang

Inventor： Charles M. Lieber ,  Yi Cui ,  Xiangfeng Duan ,  Yu Huang

IPC: H01L21/208 ,  H01L21/368

CPC classification number: H01L29/0665 ,  B01J23/50 ,  B01J23/52 ,  B01J23/72 ,  B01J35/0013 ,  B01J37/349 ,  B81C1/0019 ,  B81C1/00206 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  C30B11/00 ,  C30B25/005 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/025 ,  G11C13/04 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02573 ,  H01L21/02581 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/1602 ,  H01L29/18 ,  H01L29/20 ,  H01L29/207 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/267 ,  H01L33/06 ,  H01L33/18 ,  H01L33/20 ,  H01L51/002 ,  H01L51/0048 ,  H01L2924/0002 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S438/962 ,  Y10S977/762 ,  Y10S977/847 ,  Y10S977/858 ,  Y10S977/882 ,  Y10S977/883 ,  Y10S977/892 ,  Y10S977/936 ,  Y10T428/24 ,  H01L2924/00

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications.

公开(公告)号：US20090235134A1

公开(公告)日：2009-09-17

申请号：US12471227

申请日：2009-05-22

Applicant: Ruifeng Guo ,  Wu-Tung Cheng ,  Yu Huang

Inventor： Ruifeng Guo ,  Wu-Tung Cheng ,  Yu Huang

IPC: G01R31/3177 ,  G06F11/25 ,  G06F15/16

CPC classification number: G01R31/318544

Abstract: Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. At least some embodiments can be used to locate faults over multiple capture cycles in the scan chain.

Abstract translation: 所公开技术的实施例包括可用于产生扫描链测试模式并提高扫描链故障诊断分辨率的技术。 例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。 至少一些实施例可用于在扫描链中的多个捕获周期上定位故障。

公开(公告)号：US20090167374A1

公开(公告)日：2009-07-02

申请号：US12405905

申请日：2009-03-17

Applicant: Yu Huang ,  Wei Fu

Inventor： Yu Huang ,  Wei Fu

IPC: H03K21/00

CPC classification number: H03K23/68

Abstract: A system and method are provided for jitter-free fractional division. The method accepts a first plurality of first signal phases, each phase having a first frequency. To make the division jitter-free, a phase is selected subsequent to deselecting a previous phase selection. The selected phase is divided by the integer N, supplying a second signal with a second frequency. Using the second signal as a clock, a first plurality of counts is triggered in series, and the counts are used to select a corresponding phase. The first signal may separate neighboring phases by 90 degrees. Then, for (N+0.25), a first count triggers a second count and selects the first phase, the second count triggers a third count and selects the second phase, the third count triggers a fourth count and selects the third phase, and the fourth count trigger the first count and selects the fourth phase.

Abstract translation: 提供了一种用于无抖动分数除法的系统和方法。 该方法接受第一多个第一信号相位，每个相位具有第一频率。 为了使分频无抖动，在取消选择先前的相位选择之后选择相位。 所选择的相位除以整数N，提供具有第二频率的第二信号。 使用第二信号作为时钟，串联地触发第一多个计数，并且使用计数来选择相应的相位。 第一个信号可以将相邻相位分离90度。 然后，对于（N + 0.25），第一计数触发第二计数并选择第一相位，第二计数触发第三计数并选择第二相位，第三计数触发第四计数并选择第三相，并且 第四计数触发第一个计数并选择第四个阶段。

公开(公告)号：US20080216649A1

公开(公告)日：2008-09-11

申请号：US11715245

申请日：2007-03-06

Applicant: Yu Huang ,  Jennifer Ly ,  Tiem Aldajani ,  Richard W. Baker

Inventor： Yu Huang ,  Jennifer Ly ,  Tiem Aldajani ,  Richard W. Baker

IPC: B01D53/22

CPC classification number: B01D61/362 ,  B01D53/228 ,  B01D71/32 ,  B01D71/44 ,  C07C29/76 ,  C07C51/47 ,  Y02E50/17 ,  Y10S203/08 ,  Y10S203/09 ,  Y10S203/14 ,  C07C31/10 ,  C07C31/08 ,  C07C31/12 ,  C07C53/08

Abstract: Processes for dehydrating an organic/water solution by pervaporation or vapor separation using fluorinated membranes. The processes are particularly useful for treating mixtures containing light organic components, such as ethanol, isopropanol or acetic acid.

Abstract translation: 使用氟化膜通过全蒸发或蒸气分离使有机/水溶液脱水的方法。 该方法对于处理含有轻质有机组分如乙醇，异丙醇或乙酸的混合物特别有用。

公开(公告)号：US20080215943A1

公开(公告)日：2008-09-04

申请号：US12074162

申请日：2008-02-29

Applicant: Ruifeng Guo ,  Yu Huang ,  Wu-Tung Cheng

Inventor： Ruifeng Guo ,  Yu Huang ,  Wu-Tung Cheng

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/318525 ,  G01R31/31853 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318569

Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Abstract translation: 所公开的技术的实施例包括可用于改进扫描链测试模式生成和扫描链故障诊断解析的基于软件的技术。 例如，某些实施例可用于产生能够将扫描链缺陷隔离成单个扫描单元的高质量链诊断测试图案。 这样的实施例可用于产生“完整”测试集，即，能够将故障扫描链中的任何扫描链缺陷分离到单个扫描单元的一组链诊断测试模式。

公开(公告)号：US20070281156A1

公开(公告)日：2007-12-06

申请号：US11386080

申请日：2006-03-21

Applicant: Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: D02G3/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

公开(公告)号：US07301199B2

公开(公告)日：2007-11-27

申请号：US10196337

申请日：2002-07-16

Applicant: Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/06

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

Abstract translation: 本发明一般涉及亚微电子电路，更具体地涉及纳米尺度制品，包括可以在各种位置和各种级别选择性地掺杂的纳米线。 在一些情况下，制品可以是单晶。 纳米尺寸线可以例如沿其长度或径向掺杂，或者根据掺杂剂的掺杂剂浓度，掺杂剂的浓度或两者掺杂。 这可以用于在单个项目中提供n型和p型导电性，或者在彼此非常接近的不同项目中提供，例如在横杆阵列中。 描述了这种制品的制造和生长，以及这些制品的布置以制造电子，光电子或自旋电子器件和部件。 例如，可以掺杂半导体材料以形成n型和p型半导体区域，用于制造诸如场效应晶体管，双极晶体管，互补反相器，隧道二极管，发光二极管，传感器等的各种器件。

公开(公告)号：US07254151B2

公开(公告)日：2007-08-07

申请号：US10734086

申请日：2003-12-11

Applicant: Charles M. Lieber ,  Xiangfeng Duan ,  Yu Huang ,  Ritesh Agarwal

Inventor： Charles M. Lieber ,  Xiangfeng Duan ,  Yu Huang ,  Ritesh Agarwal

IPC: H01S5/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  G11C2213/17 ,  G11C2213/18 ,  H01S5/021 ,  H01S5/10 ,  H01S5/12 ,  H01S5/20 ,  H01S5/341 ,  H01S5/343 ,  H01S5/347 ,  Y10S977/825 ,  Y10S977/951

Abstract: This invention generally relates to nanotechnology and nanoelectronics as well as associated methods and devices. In particular, the invention relates to nanoscale optical components such as electroluminescence devices (e.g., LEDs), amplified stimulated emission devices (e.g., lasers), waveguides, and optical cavities (e.g., resonators). Articles and devices of a size greater than the nanoscale are also included. Such devices can be formed from nanoscale wires such as nanowires or nanotubes. In some cases, the nanoscale wire is a single crystal. In one embodiment, the nanoscale laser is constructed as a Fabry-Perot cavity, and is driven by electrical injection. Any electrical injection source may be used. For example, electrical injection may be accomplished through a crossed wire configuration, an electrode or distributed electrode configuration, or a core/shell configuration. The output wavelength can be controlled, for example, by varying the types of materials used to fabricate the device. One or more such nanoscale lasers may also be integrated with other nanoscale components within a device.

Abstract translation: 本发明一般涉及纳米技术和纳米电子学以及相关的方法和装置。 特别地，本发明涉及纳米尺度光学部件，例如电致发光器件（例如，LED），放大的受激发射器件（例如，激光器），波导和光学腔（例如谐振器）。 还包括尺寸大于纳米尺寸的物品和装置。 这样的器件可以由诸如纳米线或纳米管的纳米尺寸线形成。 在某些情况下，纳米线是单晶。 在一个实施例中，纳米级激光器被构造为法布里 - 珀罗腔，并且通过电注入驱动。 可以使用任何电喷射源。 例如，电注入可以通过交叉线配置，电极或分布电极配置或核/壳配置来实现。 可以例如通过改变用于制造器件的材料的类型来控制输出波长。 一个或多个这样的纳米尺度激光器也可以与器件内的其他纳米级组件集成。

公开(公告)号：US07254028B2

公开(公告)日：2007-08-07

申请号：US11269379

申请日：2005-11-08

Applicant: Hsieh-Kun Lee ,  Chun-Chi Chen ,  Shin-Hsuu Wung ,  Yu Huang

Inventor： Hsieh-Kun Lee ,  Chun-Chi Chen ,  Shin-Hsuu Wung ,  Yu Huang

IPC: H05K7/20

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic assembly includes a PCB (20), a socket (22) mounted on the PCB, a CPU (24) connected with the socket, a heat sink (10) in thermal contact with the CPU, a foldable back plate (30) attached to an underside of the PCB and a base plane (40) forming four bridges (42). The back plate includes a first piece section (32) and a second piece section (34) pivotally joined together by a pivot (36). The first and the second piece sections each comprise two legs inserted into two corresponding bridges. Screws are used to extend through the heat sink, the PCB, the bridges to threadedly engage with the legs of the back plate, respectively. The pivot is located under a part of the PCB at which the CPU is mounted.

Abstract translation: 电子组件包括PCB（20），安装在PCB上的插座（22），与插座连接的CPU（24），与CPU热接触的散热器（10），可折叠背板（30） 附接到PCB的下侧和形成四个桥（42）的基面（40）。 后板包括通过枢轴（36）枢轴连接在一起的第一片段（32）和第二片段（34）。 第一和第二片段各自包括插入到两个对应的桥中的两个腿。 螺丝用于延伸穿过散热片，PCB，桥接件分别与背板的腿部螺纹接合。 枢轴位于安装有CPU的PCB的一部分下方。