利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

1659 records (took 0.029 seconds)

    Intra-chassis device multi-management domain system
    95.
    发明授权
    Intra-chassis device multi-management domain system 有权

    公开(公告)号：US11775465B2

    公开(公告)日：2023-10-03

    申请号：US17492936

    申请日：2021-10-04

    Applicant: Dell Products L.P.

    Inventor： Andrew Butcher ,  Shawn Joel Dube

    IPC: G06F13/40 ,  G06F13/42 ,  G06F21/44

    CPC classification number: G06F13/405 ,  G06F13/4068 ,  G06F13/4221 ,  G06F21/44 ,  G06F2213/0026 ,  G06F2221/2141

    Abstract: An intra-chassis device multi-management domain system includes a chassis housing a host processing system connected to first device(s), a secondary processing system connected to second device(s), and a management system connected to the first and second device(s). The management system may receive a first request for management access including first management domain access credentials, determine that the first management domain access credentials allow first access to a host domain associated with the host processing system and, in response, provide the first access to the first device(s) connected to the host processing system. The management system may also receive a second request for management access that includes second management domain access credentials, determine that the second management domain access credentials allow second access to a secondary domain associated with the secondary processing system and, in response, provide the second access to the second device(s) connected to the secondary processing system.

    Encoder and decoder of forward error correction (FEC) codec
    96.
    发明授权
    Encoder and decoder of forward error correction (FEC) codec 有权

    公开(公告)号：US11770138B2

    公开(公告)日：2023-09-26

    申请号：US16900637

    申请日：2020-06-12

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary

    IPC: H03M13/00 ,  G06F13/42 ,  H03M13/15

    CPC classification number: H03M13/6502 ,  G06F13/4282 ,  G06F2213/0026 ,  H03M13/1575

    Abstract: Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.

    Storage system boot method and apparatus, and computer-readable storage medium
    97.
    发明授权
    Storage system boot method and apparatus, and computer-readable storage medium 有权

    公开(公告)号：US11768736B2

    公开(公告)日：2023-09-26

    申请号：US17920844

    申请日：2021-01-27

    Applicant: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

    Inventor： Xingping Qiu

    IPC: G06F11/00 ,  G06F11/14 ,  G06F9/4401 ,  G06F13/42

    CPC classification number: G06F11/1417 ,  G06F9/4411 ,  G06F13/4221 ,  G06F2201/805 ,  G06F2213/0026

    Abstract: Provided are a storage system boot method and apparatus, and a computer-readable storage medium. The method includes: determining a configuration space by a bridge device; during booting a Basic Input Output System, after an initialization of a Peripheral Component Interconnect Express (PCIe) device is detected, determining, by connection information read from the configuration space, whether the preset hardware device is connected; if YES, continuing booting until finished; if NO, sending a reconnection instruction to stabilize a speed of a PCIe hardware link; when a number of the reconnection instruction sent is greater than a first preset value and the preset hardware device fails to be connected, sending a system reboot instruction; and when the number is less than the first preset value, continuing to determine whether the preset hardware device is connected after waiting for a preset duration.

    Transaction ordering management
    100.
    发明授权
    Transaction ordering management 有权

    公开(公告)号：US11748285B1

    公开(公告)日：2023-09-05

    申请号：US16452233

    申请日：2019-06-25

    Applicant: Amazon Technologies, Inc.

    Inventor： Roi Ben Haim ,  Guy Nakibly ,  Adi Habusha ,  Simaan Bahouth

    IPC: G06F13/38 ,  G06F9/455 ,  G11C7/10 ,  H04L69/22

    CPC classification number: G06F13/387 ,  G06F9/45533 ,  G11C7/1006 ,  H04L69/22 ,  G06F2213/0026

    Abstract: Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

Patent Agency Ranking