公开(公告)号：US20180308933A1

公开(公告)日：2018-10-25

申请号：US16022737

申请日：2018-06-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Cheng Tung

IPC分类号： H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/02634 ,  H01L21/3085 ,  H01L21/76278 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

公开(公告)号：US20180286966A1

公开(公告)日：2018-10-04

申请号：US15995083

申请日：2018-05-31

申请人： UNITED MICROELECTRONICS CORP.

发明人： Li-Wei Feng ,  Shih-Hung Tsai ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/308

CPC分类号： H01L29/66545 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.

公开(公告)号：US10074720B2

公开(公告)日：2018-09-11

申请号：US15159982

申请日：2016-05-20

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC分类号： H01L21/02 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy sublayer portions comprised of Si on sidewalls of a sacrificial fin located on a substrate, the sacrificial fin is removed, leaving the semiconductor fins protruding from a top surface of the substrate. The SiGe and Si digital alloy sublayer portions are formed using isotopically enriched Si and Ge source gases to minimize isotopic mass variation in the SiGe and Si digital alloy sublayer portions.

公开(公告)号：US20180254321A1

公开(公告)日：2018-09-06

申请号：US15907878

申请日：2018-02-28

申请人： IMEC VZW

发明人： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

CPC分类号： H01L29/0653 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823425 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775

摘要： A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US10068803B2

公开(公告)日：2018-09-04

申请号：US14722597

申请日：2015-05-27

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC分类号： H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/321 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7848

摘要： A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.

公开(公告)号：US10062614B2

公开(公告)日：2018-08-28

申请号：US15638589

申请日：2017-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

摘要： The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

公开(公告)号：US10056383B2

公开(公告)日：2018-08-21

申请号：US15446295

申请日：2017-03-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Hou-Yu Chen ,  Yong-Yan Lu

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/49 ,  H01L21/20 ,  H01L21/336 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

摘要： A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20180233500A1

公开(公告)日：2018-08-16

申请号：US15789217

申请日：2017-10-20

申请人： International Business Machines Corporation

发明人： Kangguo Cheng

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78651 ,  H01L29/78696

摘要： Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby. form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins.

公开(公告)号：US20180197789A1

公开(公告)日：2018-07-12

申请号：US15576396

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： GLENN A. GLASS ,  YING PANG ,  NABIL G. MISTKAWI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  HUANG-LIN CHAO

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/6681

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US10020230B2

公开(公告)日：2018-07-10

申请号：US15284153

申请日：2016-10-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chin Kuo ,  Hsien-Ming Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L27/088 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function.