公开(公告)号：US09508833B1

公开(公告)日：2016-11-29

申请号：US14962101

申请日：2015-12-08

申请人： International Business Machines Corporation

发明人： Effendi Leobandung ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/785

摘要： A method for forming a semiconductor device comprises, forming a fin on a semiconductor substrate, forming spacers adjacent to the fin, etching to remove exposed portions of the semiconductor substrate adjacent to the spacers to form a trench adjacent to the spacers, removing the spacers, implanting dopants in the semiconductor substrate adjacent to the fin and in the trench, and performing an annealing process to diffuse the dopants in the semiconductor substrate and form a punch through stopper region below the fin that includes the dopants.

摘要翻译： 一种用于形成半导体器件的方法包括：在半导体衬底上形成翅片，形成与鳍片相邻的间隔物，蚀刻以除去与间隔物相邻的半导体衬底的暴露部分，以形成与间隔物相邻的沟槽， 在半导体衬底中相邻于鳍片和沟槽中注入掺杂剂，并且执行退火工艺以使半导体衬底中的掺杂剂扩散，并在包括掺杂剂的鳍片之下形成穿过阻挡区域的穿孔。

公开(公告)号：US09502562B2

公开(公告)日：2016-11-22

申请号：US14945912

申请日：2015-11-19

申请人： International Business Machines Corporation

发明人： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7841 ,  H01L29/785

摘要： Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed over the fin mask structures. Employing the disposable gate structure and the gate spacer as an etch mask, physically exposed portions of the fin mask structures and the semiconductor material portion are removed by an etch. A source region and a drain region are formed by selective epitaxy of a semiconductor material from physically exposed surfaces of the crystalline insulator layer. The disposable gate structure is removed selective to the source region and the drain region. Semiconductor fins are formed by anisotropically etching portions of the semiconductor material portion, employing the gate spacer and the fin mask structures as etch masks. A gate dielectric and a gate electrode are formed within the gate cavity.

公开(公告)号：US09502541B2

公开(公告)日：2016-11-22

申请号：US14604401

申请日：2015-01-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Georgios Vellianitis ,  Mark van Dal ,  Blandine Duriez ,  Richard Kenneth Oxland

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088

CPC分类号： H01L29/41791 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin.

摘要翻译： 提供了一种鳍状场效应晶体管（FinFET）器件的鳍结构。 该器件包括衬底，设置在衬底上的第一半导体材料，设置在衬底上并形成在第一半导体材料的相对侧上的浅沟槽隔离（STI）区域，以及形成第一鳍片和第二半导体材料的第二半导体材料 翅片设置在STI区域上，第一鳍片与第二鳍片间隔开第一半导体材料的宽度。 翅片结构可以用于通过形成在第一鳍片上形成的栅极层，设置在第一鳍片和第二鳍片之间的第一半导体材料的顶表面和第二鳍片来形成FinFET器件。

公开(公告)号：US09495506B2

公开(公告)日：2016-11-15

申请号：US14733332

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Hsin Chen ,  Kai-Ming Liu

IPC分类号： G06F17/50 ,  H01L29/00 ,  H01L29/66

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/12 ,  H01L29/00 ,  H01L29/6681

摘要： Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

摘要翻译： 使用finFET标准单元结构验证标准单元布局的方法，其中多晶硅在单元边缘。 使用finFET晶体管来限定标准单元。 多晶硅虚拟结构形成在标准单元的有效区域的边缘上。 其中形成两个标准单元邻接单个多晶硅虚拟结构。 在设计流程中，形成标准单元的预布局网表示意图，其不包括对应于多晶硅虚拟结构的器件。 在使用标准单元形成设备布局的自动放置和布线处理之后，提取包括对应于多晶硅虚拟结构的MOS器件的布局布线图示意图。 然后执行布局与原理图比较，但是在比较期间，对应于多晶硅虚拟结构的MOS器件从布局后网络表中被过滤，并且不进行比较。 公开了另外的方法。

公开(公告)号：US20160322477A1

公开(公告)日：2016-11-03

申请号：US15208393

申请日：2016-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Gin-Chen HUANG ,  Tzu-Hsiang HSU ,  Chia-Jung HSU ,  Feng-Cheng YANG ,  Teng-Chun TSAI

IPC分类号： H01L29/66 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

摘要： A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

摘要翻译： 半导体器件包括用于第一鳍式场效应晶体管（FET）的第一鳍结构。 第一鳍结构包括从基板突出的第一基底层，设置在第一基底层上的第一中间层和设置在第一中间层上的第一沟道层。 第一翅片结构还包括由防止下层氧化的材料制成的第一保护层。 第一沟道层由SiGe制成，第一中间层包括设置在第一基极层上的第一半导体（例如，SiGe）层和设置在第一半导体层上的第二半导体层（例如Si）。 第一保护层覆盖第一基底层的侧壁，第一半导体层的侧壁和第二半导体层的侧壁。

公开(公告)号：US20160315087A1

公开(公告)日：2016-10-27

申请号：US15069920

申请日：2016-03-14

申请人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

发明人： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC分类号： H01L27/092 ,  H01L29/43 ,  H01L29/49

CPC分类号： H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

摘要： Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.

公开(公告)号：US09472672B2

公开(公告)日：2016-10-18

申请号：US14017564

申请日：2013-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tang Lin ,  Chih-Yu Hsu ,  Clement Hsingjen Wann ,  Chih-Sheng Chang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/76 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681

摘要： An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin.

摘要翻译： 实施例的鳍状场效应晶体管（FinFET）包括通过浅沟槽隔离（STI）区域与内部鳍片间隔开的内部翅片和外部翅片，由STI区域与外部翅片间隔开的隔离翅片，隔离件 翅片，其包括主体部分，隔离氧化物和蚀刻停止层，所述蚀刻停止层插入在主体部分和隔离氧化物之间以及STI区域和隔离氧化物之间，以及形成在内部翅片上的栅极，外部 鳍和隔离鳍。

公开(公告)号：US09472643B2

公开(公告)日：2016-10-18

申请号：US14595756

申请日：2015-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L21/28 ,  H01L21/324 ,  H01L29/423 ,  H01L21/321

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/32055 ,  H01L21/321 ,  H01L21/324 ,  H01L29/4232 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/6681

摘要： A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.

公开(公告)号：US09472620B1

公开(公告)日：2016-10-18

申请号：US14846404

申请日：2015-09-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

发明人： Sheng-chen Wang ,  Sai-Hooi Yeong ,  Tsung-Chieh Hsiao

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6681 ,  H01L29/7851

摘要： In a method for manufacturing a semiconductor device, a first semiconductor layer is formed over substrate. An etching stop layer is formed over the first semiconductor layer. A dummy layer is formed over the etching stop layer. Isolation regions are formed in the dummy layer, the etching stop layer and the first semiconductor layer. The dummy layer and the etching stop layer between the isolation regions are removed to form a space. The first semiconductor layer is exposed in the space. A second semiconductor layer is formed over the first semiconductor layer in the space. A third semiconductor layer is formed over the second semiconductor layer in the space. The isolation regions are recessed so that an upper portion of the third semiconductor layer is exposed.

摘要翻译： 在制造半导体器件的方法中，在衬底上形成第一半导体层。 在第一半导体层上形成蚀刻停止层。 在蚀刻停止层上形成虚设层。 在虚设层，蚀刻停止层和第一半导体层中形成隔离区。 去除隔离区域之间的虚设层和蚀刻停止层以形成空间。 第一半导体层暴露在空间中。 在该空间中的第一半导体层上形成第二半导体层。 在该空间中的第二半导体层上形成第三半导体层。 隔离区域是凹进的，使得第三半导体层的上部被暴露。

公开(公告)号：US09465901B2

公开(公告)日：2016-10-11

申请号：US14739108

申请日：2015-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Sheng Ke ,  Jia-Rong Hsu ,  Hung-Lung Lin ,  Wen-Ju Yang

IPC分类号： G06F17/00 ,  G06F17/50 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/78 ,  H01L27/088

CPC分类号： G06F17/5072 ,  G06F2217/12 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  Y02P90/265

摘要： A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

摘要翻译： 方法实施例包括由处理器识别集成电路（IC）布局中的空区域，其中空区域是不包括任何活动鳍片的区域。 该方法还包括提供标准虚拟鳍片单元并形成扩展的虚拟鳍片单元。 标准虚拟鳍片单元包括多个隔板。 扩展的虚拟鳍片单元大于标准虚拟鳍片单元，并且扩展的虚拟鳍片单元包括多个分区中的每一个的整数倍。 空的区域填充有多个虚拟鳍片单元，其中多个虚拟鳍片单元包括扩展的虚拟鳍片单元。 多个虚拟鳍片单元在IC中实现。