公开(公告)号：US20240113177A1

公开(公告)日：2024-04-04

申请号：US17957887

申请日：2022-09-30

申请人： Intel Corporation

发明人： Sukru Yemenicioglu ,  Quan Shi ,  Marni Nabors ,  Charles H. Wallace ,  Xinning Wang ,  Tahir Ghani ,  Andy Chih-Hung Wei ,  Mohit K. Haran ,  Leonard P. Guler ,  Sivakumar Venkataraman ,  Reken Patel ,  Richard Schenker

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

摘要： An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

公开(公告)号：US20240113164A1

公开(公告)日：2024-04-04

申请号：US18151792

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Heng-Chia Su ,  Li-Fong Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/76224 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

摘要： A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.

公开(公告)号：US20240113107A1

公开(公告)日：2024-04-04

申请号：US17957821

申请日：2022-09-30

申请人： Intel Corporation

发明人： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Marni Nabors ,  Xinning Wang

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/66795 ,  H01L29/7851

摘要： An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.

公开(公告)号：US20240107736A1

公开(公告)日：2024-03-28

申请号：US18180968

申请日：2023-03-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Wei Wu ,  Hsin-Che Chiang ,  Jeng-Ya Yeh

IPC分类号： H10B10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC分类号： H10B10/125 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7851

摘要： An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, forming a high-k metal gate (HKMG) structure over the first semiconductor fin and the second semiconductor fin, forming a trench to separate the HKMG structure into two portions, conformally depositing a first dielectric layer in the trench, depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen, and planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench.

公开(公告)号：US20240105555A1

公开(公告)日：2024-03-28

申请号：US18152385

申请日：2023-01-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Satyabrata DASH ,  Jian-Sing LI ,  Hui-Zhong ZHUANG

IPC分类号： H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/481 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes first and second gate structures, a metallization layer, and first and second tie-off contacts. The first and second gate structures extend substantially along a first direction and are aligned with each other substantially along the first direction. The metallization layer includes a Vdd line, a Vss line, metal lines between the Vdd line and the Vss line and extending substantially along a second direction different from the first direction. The first tie-off contact overlaps an intersection of the first gate structure and a first one of the Vdd line and the Vss line from a top view. The second tie-off contact overlaps an intersection of the second gate structure and a first one of the metal lines from the top view, wherein said first one of the metal lines is adjacent to a second one of the Vdd line and the Vss line.

公开(公告)号：US11943920B2

公开(公告)日：2024-03-26

申请号：US17468637

申请日：2021-09-07

申请人： UNITED MICROELECTRONICS CORP.

发明人： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC分类号： H01L27/11531 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/42 ,  H10B43/40

CPC分类号： H10B41/42 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H10B43/40

摘要： A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

公开(公告)号：US20240097006A1

公开(公告)日：2024-03-21

申请号：US18508367

申请日：2023-11-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alexander Reznicek ,  Takashi Ando ,  Jingyun Zhang ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/7851

摘要： A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

公开(公告)号：US20240096893A1

公开(公告)日：2024-03-21

申请号：US18518670

申请日：2023-11-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Yao Lin ,  Chao-Cheng Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Wei-Liang Lu ,  Kuei-Yu Kao

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

公开(公告)号：US11935890B2

公开(公告)日：2024-03-19

申请号：US17718182

申请日：2022-04-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Yi Peng ,  Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Ling-Yen Yeh ,  Carlos H. Diaz ,  Tung-Ying Lee

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H04L9/40 ,  H04L67/303 ,  H04L67/306

CPC分类号： H01L27/0924 ,  H01L21/0228 ,  H01L21/76897 ,  H01L23/53295 ,  H01L23/5384 ,  H01L27/1248 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7851 ,  H01L29/786 ,  H01L29/78681 ,  H01L29/78684 ,  H04L63/0853 ,  H04L67/303 ,  H04L67/306 ,  H01L29/41791 ,  H01L2029/7858

摘要： In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

公开(公告)号：US20240088266A1

公开(公告)日：2024-03-14

申请号：US18511711

申请日：2023-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsueh-Chang SUNG ,  Kun-Mu LI

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3085 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/0653

摘要： A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.