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公开(公告)号:US09748398B2
公开(公告)日:2017-08-29
申请号:US14443882
申请日:2014-09-28
发明人: Qianqian Bu , Wei Guo
IPC分类号: H01L29/10 , H01L29/786 , H01L21/28 , H01L21/02 , H01L21/027 , H01L21/265 , H01L21/3105 , H01L21/3213 , H01L27/12 , H01L29/167 , H01L29/423 , H01L29/66
CPC分类号: H01L29/78675 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02675 , H01L21/0273 , H01L21/0274 , H01L21/26513 , H01L21/28 , H01L21/31058 , H01L21/32134 , H01L21/32139 , H01L27/1222 , H01L27/1248 , H01L27/1274 , H01L27/1288 , H01L29/167 , H01L29/42372 , H01L29/42384 , H01L29/66757 , H01L29/786 , H01L29/78621
摘要: A thin film transistor, its manufacturing method, and a display device are provided. The method comprises: forming a gate metal layer (35), forming a step-like gate structure (352) by one patterning process; performing a first ion implantation procedure to forming a first heavily doped area (39a) and a second heavily doped area (39b), the first heavily doped area (39a) being separated apart from the second heavily doped area (39b) by a first length; forming a gate electrode (353) from the step-like gate structure (352); performing a second ion implantation procedure to form a first lightly doped area (38a) and a second lightly doped area (38b), the first lightly doped area (38a) being separated apart from the second lightly doped area (38b) by a second length less than the first length. By the above method, the process for manufacturing the LTPS TFT having the lightly doped source/drain structure can be simplified.
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公开(公告)号:US09747962B2
公开(公告)日:2017-08-29
申请号:US15125658
申请日:2015-03-05
IPC分类号: G11C7/22 , G11C11/405 , H01L29/786 , G11C11/56 , G11C27/00 , H01L27/06 , H01L27/12 , G11C5/14 , H01L27/108 , H01L27/1156 , H01L27/088
CPC分类号: G11C7/22 , G11C5/14 , G11C11/405 , G11C11/565 , G11C27/005 , H01L27/0688 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1225 , H01L29/786
摘要: A semiconductor device which can write and read multilevel data is provided. A node connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read.
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公开(公告)号:US20170235173A1
公开(公告)日:2017-08-17
申请号:US15509526
申请日:2015-08-31
发明人: Sumio KATOH , Naoki UEDA
IPC分类号: G02F1/1368 , H01L29/786 , H01L27/12 , G02F1/1362 , G02F1/1343
CPC分类号: G02F1/1368 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F2001/134372 , G02F2001/136218 , G02F2201/121 , G02F2201/123 , G02F2202/02 , G02F2202/10 , H01L21/28 , H01L27/1225 , H01L27/1248 , H01L29/786 , H01L29/7869
摘要: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.
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公开(公告)号:US20170235172A1
公开(公告)日:2017-08-17
申请号:US15434070
申请日:2017-02-16
申请人: Innolux Corporation
发明人: Te-Yi Chen , Han-Tsung Su , Hsin-Hung Lin , Ker-Yih Kao
IPC分类号: G02F1/1368 , H01L29/45 , H01L29/417 , G02F1/1343 , G02F1/1362
CPC分类号: G02F1/1368 , G02F1/136286 , G02F2001/134318 , G02F2001/134345 , G02F2001/136236 , H01L29/45 , H01L29/66969 , H01L29/786
摘要: An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.
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公开(公告)号:US20170230653A1
公开(公告)日:2017-08-10
申请号:US15502975
申请日:2015-08-11
CPC分类号: H04N17/004 , G01M11/00 , G02F1/1368 , G02F2001/136254 , G09F9/00 , H01L27/283 , H01L29/786 , H01L29/808 , H01L29/812 , H01L51/0031 , H01L51/0508 , H01L51/0541 , H01L51/0545
摘要: To provide an inspection device and an inspection method which are capable of detecting a disconnection defect in an organic TFT array and/or evaluating a variation in the output properties and response speed of each organic TFT element. There are provided a device and a method of optically measuring the presence or absence of the accumulation of carriers in an organic semiconductor thin film which provides a channel layer of an organic TFT element. A source and a drain in each organic TFT are short-circuited to each other, a voltage is turned on and turned off in a predetermined period between this and a gate, and images before and after application of the voltage are captured in synchronization with the predetermined period while radiating monochromatic light, to obtain a differential image.
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公开(公告)号:US20170222061A1
公开(公告)日:2017-08-03
申请号:US14778607
申请日:2015-06-24
发明人: Wenshuai Guo , Xing Ming , Zhiyuan Shen
IPC分类号: H01L29/786 , H01L29/423 , H01L29/66 , H01L27/12
CPC分类号: H01L29/78675 , H01L27/12 , H01L27/1222 , H01L27/1288 , H01L29/42384 , H01L29/6675 , H01L29/66757 , H01L29/786 , H01L29/78606 , H01L29/78645 , H01L29/78696
摘要: The present invention provides a manufacture method of a TFT substrate structure and a TFT substrate structure. In the manufacture method of the TFT substrate structure, as manufacturing the gate, a plurality of metal sections distributed in spaces are formed at two sides of the gate, and the gate and the plurality of metal sections are employed to be a mask to implement ion implantation to the polysilicon layer. In the TFT substrate structure according to the present invention, the undoped areas are formed among the n-type heavy doping areas while forming the n-type heavy doping areas at the polysilicon layer.
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公开(公告)号:US20170221928A1
公开(公告)日:2017-08-03
申请号:US14779545
申请日:2015-08-13
发明人: Xiaoxiao WANG , Peng DU , Cong WANG
IPC分类号: H01L27/12 , H01L29/66 , H01L21/3213 , H01L29/45 , H01L29/786 , H01L21/02
CPC分类号: H01L27/1222 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L21/02164 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/22 , H01L21/26513 , H01L21/32133 , H01L27/1218 , H01L27/124 , H01L27/127 , H01L27/1288 , H01L29/458 , H01L29/66757 , H01L29/786 , H01L29/78633 , H01L29/78675
摘要: An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.
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公开(公告)号:US20170219863A1
公开(公告)日:2017-08-03
申请号:US15487587
申请日:2017-04-14
发明人: Xiangyang XU
IPC分类号: G02F1/1368 , G02F1/1343 , H01L29/786 , H01L27/12 , H01L29/49 , G02F1/1333 , H01L29/66
CPC分类号: G02F1/1368 , G02F1/133345 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F2001/13685 , G02F2201/123 , G02F2202/10 , H01L21/77 , H01L27/12 , H01L27/1225 , H01L27/1248 , H01L29/4908 , H01L29/66969 , H01L29/786 , H01L29/78633 , H01L29/78648 , H01L29/78693
摘要: A thin film transistor array substrate includes a bottom gate disposed on a substrate and a bottom gate insulating layer covering the bottom gate, a semiconductor oxide layer disposed on the bottom gate insulating layer and an etch blocking layer covering the semiconductor oxide layer and including a first via, a drain disposed on the etch blocking layer and contacting with the semiconductor oxide layer through the first via and an insulating protection layer covering the drain, a second via arranged in the insulating protection layer, the etch blocking layer and the bottom gate insulating layer, a top gate disposed on insulating protection layer and contacting with the bottom gate through the second via. A method for manufacturing the thin film transistor array substrate is also disclosed. The thin film transistor prevents the threshold voltage thereof from being drifted in a case of negative bias illumination stress (NBIS).
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公开(公告)号:US20170199466A1
公开(公告)日:2017-07-13
申请号:US15472233
申请日:2017-03-28
发明人: Jingfeng XUE , Xin ZHANG , Gui CHEN
IPC分类号: G03F7/20 , H01L29/786 , H01L27/12
CPC分类号: G03F7/70058 , G02F1/1368 , G02F2202/104 , H01L21/0274 , H01L21/223 , H01L21/2652 , H01L21/266 , H01L21/67011 , H01L27/1222 , H01L27/127 , H01L27/1285 , H01L27/1288 , H01L29/66492 , H01L29/66598 , H01L29/66757 , H01L29/786 , H01L29/78621 , H01L29/78675
摘要: A device for manufacturing an array substrate includes an exposure device for using a halftone mask to form a photoresist pattern layer on a gate insulation layer of a substrate. A polysilicon pattern layer is disposed on the substrate. A gate insulation layer covers the polysilicon pattern layer. The photoresist pattern layer includes a hollow portion corresponding to a heavily doping region of the polysilicon pattern layer, a first photoresist portion corresponding to a lightly doping region of the polysilicon pattern layer, and a second photoresist portion corresponding to an undoped region of the polysilicon pattern layer. The first photoresist portion is thinner than the second photoresist portion. A doping device is used for performing one doping process to the polysilicon pattern layer such that the heavily doping region and the lightly doping region are formed simultaneously.
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公开(公告)号:US09704971B2
公开(公告)日:2017-07-11
申请号:US14963397
申请日:2015-12-09
申请人: GLOBALFOUNDRIES Inc.
IPC分类号: H01L29/66 , H01L29/786
CPC分类号: H01L29/4983 , H01L29/0649 , H01L29/0847 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/66772 , H01L29/7838 , H01L29/786 , H01L29/78654
摘要: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.
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