公开(公告)号：US09264076B2

公开(公告)日：2016-02-16

申请号：US14177371

申请日：2014-02-11

Applicant: STMICROELECTRONICS SA ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Didier Belot ,  Yann Deval ,  Francois Rivet

IPC: G06F1/04 ,  H03K3/00 ,  H04B1/00 ,  H04B1/403 ,  H04B1/04

CPC classification number: H04B1/0014 ,  H04B1/406 ,  H04B2001/0491

Abstract: A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device.

Abstract translation: 一种用于产生信号的装置，包括：平衡 - 不平衡转换器; 以及能够在所述平衡 - 不平衡变换器的第一接入终端上总和的电流，代表在所述设备的第一输入端子上接收的信号的电流，以及在所述平衡 - 不平衡变换器的第二接入终端上的总和的电流， 装置。

公开(公告)号：US09257754B2

公开(公告)日：2016-02-09

申请号：US13332031

申请日：2011-12-20

Applicant: Jean-Francois Carpentier ,  Sebastien Pruvost ,  Patrice Garcia ,  Pierre Busson ,  Pierre Dautriche

Inventor： Jean-Francois Carpentier ,  Sebastien Pruvost ,  Patrice Garcia ,  Pierre Busson ,  Pierre Dautriche

IPC: H01Q21/00 ,  H01Q23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01Q21/0087 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/16225 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01Q19/005 ,  H01Q19/10 ,  H01Q19/185 ,  H01Q21/0025 ,  H01Q21/0093 ,  H01Q23/00 ,  H01L2924/00

Abstract: A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

Abstract translation: 一种毫米波收发器，包括形成插入件的板，其具有支撑互连网络的上表面，并且其下表面旨在通过凸块组装在印刷电路板上; 组装在所述插入件的上表面上的集成电路芯片; 由形成在插入件的上表面上的轨道制成的天线; 以及在每个天线前面的印刷电路板的上表面上的反射器，考虑到插入材料的介电常数，每个天线和反射板之间的有效距离在波长的四分之一左右 。

公开(公告)号：US09257526B2

公开(公告)日：2016-02-09

申请号：US14313836

申请日：2014-06-24

Applicant: STMicroelectronics SA

Inventor： Pierre Boulenc

IPC: H01L29/66 ,  H01L21/8249 ,  H01L29/732 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/66333 ,  H01L21/8249 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/7325 ,  H01L29/7395

Abstract: The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.

Abstract translation: 本公开涉及一种用于制造双极晶体管的方法。 该方法形成沟槽以将第一区域与半导体晶片中的第二区域隔离，并将这些区域与晶片的其余部分隔离。 该方法在第二区域中形成第一P掺杂阱，并且在第一区域中通过P掺杂产生第二阱和第三阱的集电极区。 第二个井与沟槽下面的第一个井接触。 该方法还在集电极区域和晶片表面上产生N掺杂的基极阱，并在第一区域上形成CMOS晶体管栅极并限定第三区域和第四区域。 该方法还在第一阱中形成P +掺杂的集电极接触区，在第三区中形成P +掺杂的发射极区，并在第四区中形成N +掺杂的基极接触区。

公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09236407B2

公开(公告)日：2016-01-12

申请号：US14144168

申请日：2013-12-30

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： François Roy ,  Yvon Cazaux

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14656

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract translation: 布置在半导体衬底的内部和顶部的具有多个像素的图像传感器，每个像素包括：感光区域，读取区域和在感光区域和读取区域之间延伸的存储区域; 至少一个第一绝缘垂直电极，其在所述基板中在所述光敏区域和所述存储区域之间延伸; 以及在所述存储区域和所述读取区域之间的所述衬底中延伸的至少一个第二绝缘垂直电极。

公开(公告)号：US09231642B2

公开(公告)日：2016-01-05

申请号：US14191037

申请日：2014-02-26

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frederic Gianesello

IPC: H04B1/44 ,  H04B1/40 ,  H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/24 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  H03F3/20

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract translation: 一个由1到2个分路器组成的多通道分路器。 第一个1到2个分配器的输入端定义了多通道分离器的输入。 1至2个分离器电气串联连接。 1到2个分路器的第一个相应的输出定义了多通道分路器的输出端子。

公开(公告)号：US09178538B2

公开(公告)日：2015-11-03

申请号：US13300291

申请日：2011-11-18

Applicant: Nicolas Delaunay ,  Eric Kerherve ,  Nathalie Deltimple ,  Didier Belot

Inventor： Nicolas Delaunay ,  Eric Kerherve ,  Nathalie Deltimple ,  Didier Belot

IPC: H04L25/49 ,  H04B1/04 ,  H03F1/32 ,  H03F3/24

CPC classification number: H04B1/0475 ,  H03F1/3247 ,  H03F1/3294 ,  H03F3/24 ,  H03F2200/336

Abstract: The invention concerns a circuit for multi-standard wireless RF transmission comprising: input circuitry (302 to 314) for generating a transmission signal (IT(t), QT(t)) based on an input data signal (I, Q); a power amplifier (316) adapted to amplify said transmission signal to provide an output signal (S(t)) for transmission via at least one antenna; and feedback circuitry (320 to 340) comprising at least one variable low-pass filter (334, 336) for generating a feedback signal (IFB, QFB) based on said output signal, wherein said input circuitry further comprises pre-distortion circuitry (302) adapted to modify said input data signal (I, Q) based on said feedback signal.

Abstract translation: 本发明涉及一种用于多标准无线RF传输的电路，包括：用于基于输入数据信号（I，Q）产生传输信号（IT（t），QT（t））的输入电路（302至314）; 功率放大器（316），适于放大所述传输信号以提供用于经由至少一个天线传输的输出信号（S（t））; 以及包括至少一个可变低通滤波器（334,336）的反馈电路（320至340），用于基于所述输出信号产生反馈信号（IFB，QFB），其中所述输入电路还包括预失真电路 ）适于基于所述反馈信号修改所述输入数据信号（I，Q）。

公开(公告)号：US09099366B2

公开(公告)日：2015-08-04

申请号：US13529045

申请日：2012-06-21

Applicant: Francois Roy ,  Julien Michelot

Inventor： Francois Roy ,  Julien Michelot

IPC: H01L27/146 ,  H01L31/0352

CPC classification number: H01L27/14603 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/1464 ,  H01L31/0352

Abstract: A photosite is formed in a semiconductor substrate and includes a photodiode confined in a direction orthogonal to the surface of the substrate. The photodiode includes a semiconductor zone for storing charge that is formed in an upper semiconductor region having a first conductivity type and includes a main well of a second conductivity type opposite the first conductivity type and laterally pinned in a first direction parallel to the surface of the substrate. The photodiode further includes an additional semiconductor zone including an additional well having the second conductivity type that is buried under and makes contact with the main well.

Abstract translation: 在半导体衬底中形成有一个光电子结构，并包括一个限制在与衬底表面正交的方向上的光电二极管。 光电二极管包括用于存储形成在具有第一导电类型的上半导体区域中的电荷的半导体区，并且包括与第一导电类型相反的第二导电类型的主阱，并且在与第一导电类型的表面平行的第一方向上横向固定 基质。 光电二极管还包括另外的半导体区域，该半导体区域包括具有第二导电类型的另外的阱，该第二导电类型被埋在主阱中并与主阱接触。

公开(公告)号：US20150206662A1

公开(公告)日：2015-07-23

申请号：US14416978

申请日：2013-07-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Yann Lamy ,  Olivier Guiller ,  Sylvain Joblot

IPC: H01G4/30 ,  H05K1/18

CPC classification number: H01G4/306 ,  H01G4/33 ,  H01G4/38 ,  H01L28/87 ,  H01L28/91 ,  H05K1/181

Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

Abstract translation: 一种用于在基板的一部分中制造电容器堆叠的方法，所述方法包括：从所述基板的上表面沿着所述基板的所述部分的厚度形成空腔，将有助于所述电容器堆叠的多个层沉积到所述基板上 空腔的壁和上表面上，并且从层中去除物质直到达到上表面的表面。 腔的形成包括形成至少一个沟槽，并且与每个沟槽相关联，至少一个盒子。 至少一个沟槽包括通向盒子的沟槽出口。 盒子包括在上表面开口的盒子出口，盒子出口的形状大于沟槽出口。

公开(公告)号：US09052560B2

公开(公告)日：2015-06-09

申请号：US13920206

申请日：2013-06-18

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Michel Marty ,  Flavien Hirigoyen ,  Josep Segura Puchades ,  Hélène Wehbe-Alause ,  Umberto Rossini

IPC: H01L33/36 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136277 ,  G02F2001/136281 ,  H01L33/36

Abstract: A nanoprojector panel formed of an array of cells, each cell including a liquid crystal layer between upper and lower transparent electrodes, a MOS control transistor being arranged above the upper electrode, each transistor being covered with at least three metallization levels. The transistor of each cell extends in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of the assembly. The upper metallization level extends above the transistors of each the assembly of four adjacent cells. The panel includes, for each assembly of four adjacent cells, a first conductive ring surrounding the transistors, the first ring extending from the lower metallization level to the upper electrode of each cell, with an interposed insulating material.

Abstract translation: 一种由单元阵列形成的纳米光电板面板，每个单元包括上透明电极和下透明电极之间的液晶层，MOS控制晶体管布置在上电极上方，每个晶体管被覆盖有至少三个金属化水平。 每个单元的晶体管延伸在单元的角部，使得四个相邻单元的组件的晶体管被​​布置在组件的中心区域中。 上部金属化水平延伸到四个相邻单元的每个组件的晶体管之上。 对于四个相邻电池的每个组件，面板包括围绕晶体管的第一导电环，第一环从下部金属化层延伸到每个电池的上部电极，并具有插入的绝缘材料。