公开(公告)号：US20100184260A1

公开(公告)日：2010-07-22

申请号：US12357057

申请日：2009-01-21

Applicant: Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

Inventor： Tien-Ying Luo ,  Gauri V. Karve ,  Daniel G. Tekleab

IPC: H01L21/82 ,  H01L21/77 ,  H01L21/04 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).

Abstract translation: 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化物区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。

公开(公告)号：US07700499B2

公开(公告)日：2010-04-20

申请号：US12008607

申请日：2008-01-11

Applicant: Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

Inventor： Kurt H. Junker ,  Paul A. Grudowski ,  Xiang-Zheng Bo ,  Tien Ying Luo

IPC: H01L21/31

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.

Abstract translation: 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。

公开(公告)号：US20100081290A1

公开(公告)日：2010-04-01

申请号：US12241139

申请日：2008-09-30

Applicant: Tien Ying Luo ,  Olubunmi O. Adetutu

Inventor： Tien Ying Luo ,  Olubunmi O. Adetutu

IPC: H01L21/285

CPC classification number: H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

Abstract translation: 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

公开(公告)号：US07678698B2

公开(公告)日：2010-03-16

申请号：US11744581

申请日：2007-05-04

Applicant: Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

Inventor： Xiangzheng Bo ,  Tien Ying Luo ,  Kurt H. Junker ,  Paul A. Grudowski ,  Venkat R. Kolagunta

IPC: H01L21/44

CPC classification number: H01L29/7843 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3185 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Abstract translation: 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。

公开(公告)号：US07639375B2

公开(公告)日：2009-12-29

申请号：US11639974

申请日：2006-12-14

Applicant: Sanjay Yedur ,  Shifang Li ,  Youxian Wen ,  Wei Liu ,  Hanyou Chu ,  Ying Ying Luo

Inventor： Sanjay Yedur ,  Shifang Li ,  Youxian Wen ,  Wei Liu ,  Hanyou Chu ,  Ying Ying Luo

IPC: G01B11/14

CPC classification number: G06T7/0004 ,  G03F1/84 ,  G03F7/70591 ,  G03F7/70941 ,  G06T2207/30148

Abstract: Transmittance of a photomask is determined using optical metrology. In particular, reflectance of a portion of the photomask is determined by directing an incident beam of light at the portion of the photomask. The reflectance is determined by measuring light diffracted from the portion of the photomask. One or more geometric features of the portion of the photomask are determined using the measured light diffracted from the portion of the photomask. A wave coupling is determined using the determined one or more geometric features of the portion of the photomask. The transmittance of the photomask is determined using the determined wave coupling and the determined reflectance of the portion of the photomask.

Abstract translation: 使用光学测量法确定光掩模的透射率。 特别地，光掩模的一部分的反射率通过在光掩模的部分引导入射光束来确定。 通过测量从光掩模的部分衍射的光来确定反射率。 使用从光掩模的部分衍射的测量光来确定光掩模的该部分的一个或多个几何特征。 使用所确定的光掩模部分的一个或多个几何特征来确定波耦合。 使用确定的波耦合和所确定的光掩模的部分的反射率来确定光掩模的透射率。

公开(公告)号：US20090243669A1

公开(公告)日：2009-10-01

申请号：US12237223

申请日：2008-09-24

Applicant: JEN-SHENG TSAI ,  JI YANG ,  YING LUO

Inventor： JEN-SHENG TSAI ,  JI YANG ,  YING LUO

IPC: H03L7/00

CPC classification number: G06F1/24

Abstract: A power-on reset circuit includes a voltage-dividing circuit, a first switch and a second switch. The voltage-dividing circuit includes a first resistor and a second resistor connected in series. A first terminal of the voltage-dividing circuit is configured for connect to a power source, a second terminal of the voltage-dividing circuit is grounded. A first switch includes an input terminal, a control terminal, and an output terminal. The input terminal of the first switch is connected to the first terminal of the voltage-dividing circuit via the first resistor, and the output terminal of the first switch is grounded. A second switch includes an input terminal connected to the first terminal of the voltage-dividing circuit, a control terminal connected to the control terminal of the first switch, and an output terminal connected to a reset terminal of an electronic device.

Abstract translation: 上电复位电路包括分压电路，第一开关和第二开关。 分压电路包括串联连接的第一电阻器和第二电阻器。 分压电路的第一端子被配置为连接到电源，分压电路的第二端子接地。 第一开关包括输入端子，控制端子和输出端子。 第一开关的输入端通过第一电阻连接到分压电路的第一端，第一开关的输出端接地。 第二开关包括连接到分压电路的第一端子的输入端子，连接到第一开关的控制端子的控制端子和连接到电子设备的复位端子的输出端子。

公开(公告)号：US20090221120A1

公开(公告)日：2009-09-03

申请号：US12039361

申请日：2008-02-28

Applicant: Tien Ying Luo ,  Ning Liu ,  Mohamed S. Moosa

Inventor： Tien Ying Luo ,  Ning Liu ,  Mohamed S. Moosa

IPC: H01L21/31 ,  H01L21/336

CPC classification number: H01L21/3144 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich region is formed within and at a surface of the base oxide layer. The nitrogen-rich region overlies an oxide region in the base oxide layer. Afterwards, the semiconductor device is annealed in a dilute oxygen and hydrogen-free ambient of below 1 Torr partial pressure of the oxygen. The annealing heals bond damage in both the oxide region and the nitrogen-rich region in the base oxide layer. After annealing the semiconductor device in the dilute oxygen ambient, in-situ steam generation (ISSG) is used to grow and density the oxide region in the base oxide layer at an interface between the substrate and base oxide layer.

Abstract translation: 形成半导体器件的方法包括提供用于半导体器件的衬底。 通过在氧的存在下施加衬底的快速热氧化（RTO），在衬底上形成基底氧化物层。 在基底氧化物层的表面内和表面形成富氮区域。 富氮区域覆盖在基底氧化物层中的氧化物区域。 之后，半导体器件在氧低于1Torr分压的稀氧和无氢环境中进行退火。 该退火对基底氧化物层中的氧化物区域和富氮区域进行了愈合。 在稀氧环境中对半导体器件进行退火之后，使用原位蒸汽发生（ISSG）来生长和密集基底氧化物层中的氧化物区域，该基底氧化物层在衬底和基底氧化物层之间的界面处。

公开(公告)号：US07488805B2

公开(公告)日：2009-02-10

申请号：US11739267

申请日：2007-04-24

Applicant: Ying Luo ,  Betty Huang ,  Mary Shen ,  Pei Wen Yu

Inventor： Ying Luo ,  Betty Huang ,  Mary Shen ,  Pei Wen Yu

IPC: C07K16/00

CPC classification number: C07K14/4747 ,  A61K38/00

Abstract: The present invention is directed to novel apoptosis polypeptides such as the Apop1, Apop2, and Apop3 proteins and related molecules which are involved in modulating apoptosis and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided by the present invention are method for identifying novel compositions which modulate the biological activity of Apop1, Apop2, and Apop3, and the use of such compositions in diagnosis and treatment of disease.

Abstract translation: 本发明涉及新的凋亡多肽，例如参与调节凋亡的Apop1，Apop2和Apop3蛋白和相关分子以及编码这些多肽的核酸分子。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。 本发明还提供了鉴定调节Apop1，Apop2和Apop3的生物学活性的新组合物的方法，以及这些组合物在疾病诊断和治疗中的用途。

公开(公告)号：US07445984B2

公开(公告)日：2008-11-04

申请号：US11459837

申请日：2006-07-25

Applicant: Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

Inventor： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/36

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/32134 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract translation: 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 在半导体层上形成第一电介质层。 在第一电介质层上进行等离子体氮化。 在第一部分上形成第一多个纳米团簇，并在第二部分上形成第二多个纳米团簇。 第二组纳米团簇被去除。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。

公开(公告)号：US07420045B1

公开(公告)日：2008-09-02

申请号：US10130555

申请日：2000-11-17

Applicant: Ying Luo ,  Xiang Xu ,  Cindy Leo ,  Betty Huang ,  Mary Shen

Inventor： Ying Luo ,  Xiang Xu ,  Cindy Leo ,  Betty Huang ,  Mary Shen

IPC: C07H21/02 ,  C12P21/06 ,  C12P1/00 ,  C12N1/20

CPC classification number: C07K14/4747 ,  A61K38/00

Abstract: The present invention is directed to novel polypeptides, nucleic acids and related molecules which have an effect on or are related to the cell cycle. Also, provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided by the present invention are methods for identifying novel compositions which mediate cell cycle bioactivity, and the use of such compositions in diagnosis and treatment of disease.

Abstract translation: 本发明涉及对细胞周期有影响或与细胞周期有关的新型多肽，核酸和相关分子。 此外，本文提供的是包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及用于产生本发明多肽的方法 本发明。 本发明还提供了鉴定介导细胞周期生物活性的新型组合物的方法，以及这些组合物在疾病诊断和治疗中的应用。