中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

192 records (took 0.019 seconds)

    Low-profile hinge for an electronic device
    107.
    发明授权
    Low-profile hinge for an electronic device 有权
    电子设备的低调铰链

    公开(公告)号：US09360896B2

    公开(公告)日：2016-06-07

    申请号：US14229830

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Min Suet Lim ,  Bok Eng Cheah ,  Howe Yin Loo ,  Jackson Chung Peng Kong ,  Poh Tat Oh

    IPC: E05D3/06 ,  G06F1/16

    CPC classification number: G06F1/1681 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1637 ,  Y10T16/547

    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low-profile hinge design that includes a first segment that connects to a first element using a first coupler and to a second segment that connects to the first segment using a second coupler, where the second segment connects to a second element using a third coupler. The first coupler, the second coupler, and the third coupler may each have a first coupling arm and a second coupling arm and the first coupling arm can be offset from a plane of the second coupling arm by about five degrees to about forty-five degrees.

    Abstract translation: 本文描述的特定实施例提供了一种电子设备，例如笔记本电脑或膝上型计算机，其包括耦合到多个电子部件（其包括任何类型的组件，元件，电路等）的电路板。 电子设备的一个具体示例实现可以包括低轮廓铰链设计，其包括使用第一耦合器连接到第一元件的第一段和使用第二耦合器连接到第一段的第二段，其中第二段 段使用第三耦合器连接到第二元件。 第一耦合器，第二耦合器和第三耦合器可以各自具有第一耦合臂和第二耦合臂，并且第一耦合臂可以从第二耦合臂的平面偏移约五度至约四十五度 。

    LOW-PROFILE HINGE FOR AN ELECTRONIC DEVICE
    108.
    发明申请
    LOW-PROFILE HINGE FOR AN ELECTRONIC DEVICE 有权
    用于电子设备的低轮廓铰链

    公开(公告)号：US20150277505A1

    公开(公告)日：2015-10-01

    申请号：US14229830

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Min Suet Lim ,  Bok Eng Cheah ,  Howe Yin Loo ,  Jackson Chung Peng Kong ,  Poh Tat Oh

    IPC: G06F1/16

    CPC classification number: G06F1/1681 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1637 ,  Y10T16/547

    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low-profile hinge design that includes a first segment that connects to a first element using a first coupler and to a second segment that connects to the first segment using a second coupler, where the second segment connects to a second element using a third coupler. The first coupler, the second coupler, and the third coupler may each have a first coupling arm and a second coupling arm and the first coupling arm can be offset from a plane of the second coupling arm by about five degrees to about forty-five degrees.

    Abstract translation: 本文描述的特定实施例提供了一种电子设备，例如笔记本电脑或膝上型计算机，其包括耦合到多个电子部件（其包括任何类型的组件，元件，电路等）的电路板。 电子设备的一个具体示例实现可以包括低轮廓铰链设计，其包括使用第一耦合器连接到第一元件的第一段和使用第二耦合器连接到第一段的第二段，其中第二段 段使用第三耦合器连接到第二元件。 第一耦合器，第二耦合器和第三耦合器可以各自具有第一耦合臂和第二耦合臂，并且第一耦合臂可以从第二耦合臂的平面偏移约五度至约四十五度 。

    Semiconductor package with hybrid mold layers
    109.
    发明授权
    Semiconductor package with hybrid mold layers 有权

    公开(公告)号：US12288740B2

    公开(公告)日：2025-04-29

    申请号：US17367684

    申请日：2021-07-06

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Chia Chuan Wu ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/367 ,  H01L23/552 ,  H01L25/065

    Abstract: According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a plurality of second interconnects configured to couple the first package substrate to a printed circuit board.

    Multi-chip package with recessed memory
    110.
    发明授权
    Multi-chip package with recessed memory 有权

    公开(公告)号：US12191281B2

    公开(公告)日：2025-01-07

    申请号：US17348802

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Yang Liang Poh ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

    IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

    Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

Patent Agency Ranking