公开(公告)号：US10333519B2

公开(公告)日：2019-06-25

申请号：US16011518

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  H03K19/0175 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US10304517B2

公开(公告)日：2019-05-28

申请号：US15872848

申请日：2018-01-16

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409 ,  G11C29/02 ,  G11C11/4096

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20190114271A1

公开(公告)日：2019-04-18

申请号：US16164242

申请日：2018-10-18

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/409 ,  G11C11/4076 ,  G06F3/06

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

公开(公告)号：US10192598B2

公开(公告)日：2019-01-29

申请号：US15623261

申请日：2017-06-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C8/12 ,  G11C5/02 ,  G11C8/18 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20180011805A1

公开(公告)日：2018-01-11

申请号：US15498065

申请日：2017-04-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F13/16 ,  G11C7/22 ,  G06F12/00 ,  G11C7/10

CPC classification number: G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US09865329B2

公开(公告)日：2018-01-09

申请号：US15389409

申请日：2016-12-22

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C8/00 ,  G11C11/4093 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US09734112B2

公开(公告)日：2017-08-15

申请号：US15051282

申请日：2016-02-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/00 ,  G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US09704560B2

公开(公告)日：2017-07-11

申请号：US15242423

申请日：2016-08-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20170147263A1

公开(公告)日：2017-05-25

申请号：US15336554

申请日：2016-10-27

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/00 ,  G06F13/4273 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1075 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

公开(公告)号：US09570129B2

公开(公告)日：2017-02-14

申请号：US15081745

申请日：2016-03-25

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02 ,  G11C11/4063 ,  G11C5/04 ,  G11C11/4097 ,  G11C7/18 ,  G11C5/02

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

Abstract translation: 系统具有以飞越拓扑布置的多个存储器件，每个存储器件具有用于连接到地址和控制（RQ）总线的片上终端（ODT）电路。 每个存储器件的ODT电路包括一组一个或多个控制寄存器，用于控制RQ总线的一个或多个信号线的管芯端接。 第一存储器件包括存储第一ODT值的一个或多个控制寄存器的第一组，用于控制由第一存储器件的ODT电路终止RQ总线的一个或多个信号线，第二存储器器件包括： 存储与第一ODT值不同的第二ODT值的一个或多个控制寄存器的第二组，用于控制由第二存储器件的ODT电路终止RQ总线的一个或多个信号线。