公开(公告)号：US06982135B2

公开(公告)日：2006-01-03

申请号：US10402590

申请日：2003-03-28

申请人： Chung-Hsing Chang ,  Chien-Hung Lin ,  Burn J. Lin ,  Chia-Hui Lin ,  Chih-Cheng Chin ,  Chin-Hsiang Lin ,  Fu-Jye Liang ,  Jeng-Horng Chen ,  Bang-Ching Ho

发明人： Chung-Hsing Chang ,  Chien-Hung Lin ,  Burn J. Lin ,  Chia-Hui Lin ,  Chih-Cheng Chin ,  Chin-Hsiang Lin ,  Fu-Jye Liang ,  Jeng-Horng Chen ,  Bang-Ching Ho

IPC分类号： G03F9/00 ,  G03F7/20

CPC分类号： G03F1/20 ,  G03B27/42 ,  G03F1/00 ,  G03F7/70475

摘要： A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).

摘要翻译： 将图案从掩模转印到基板（或晶片）的方法包括将掩模生成数据文件分割成多个段。 片段包括主图案区域和缝合区域。 每个缝合区域包含各自的共同图案。 形成主图案区域的照明部分的图像。 衬底区域（或晶片区域）中的段的连接端用照明光束照射。 形成主图案区域的照明部分的图像，并且在对应于共同图案的基板区域（或晶片区域）中产生半色调灰度级剂量分布。 相邻段的共同图案在衬底区域（或晶片区域）中基本上重叠。

公开(公告)号：US06968251B2

公开(公告)日：2005-11-22

申请号：US10918413

申请日：2004-08-16

申请人： Chin-Hsiang Lin ,  Ching-Cheng Shih

发明人： Chin-Hsiang Lin ,  Ching-Cheng Shih

IPC分类号： G01N21/88 ,  G01N37/00 ,  G05B19/418 ,  G06F19/00 ,  H01L21/66

CPC分类号： G05B19/41875 ,  G05B2219/32194 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/22

摘要： A defect analysis sampling control system comprising a base setting module, a lot setting module, and a work in process (WIP) prediction module. The base setting module is used for choosing and setting a corresponding sampling rule in accordance with different semiconductor products and the lot setting module is used for choosing and setting a corresponding lot sampling rule in accordance with a product lot. The work in process (WIP) prediction module records all WIP products to provide status and progress of the WIP product. The present invention can be applied to a variety of products so as to control and adjust the sampling rule for all products more conveniently and arrange the sampling rules more flexibly.

摘要翻译： 一种缺陷分析抽样控制系统，包括基本设置模块，批量设定模块和在制品（WIP）预测模块。 基本设置模块用于根据不同的半导体产品选择和设置相应的采样规则，批量设置模块用于根据产品批次选择和设置相应的批次采样规则。 在制品（WIP）预测模块记录所有WIP产品，以提供WIP产品的状态和进度。 本发明可以应用于各种产品，以便更方便地控制和调整所有产品的采样规则，并更灵活地布置采样规则。

公开(公告)号：US20050164098A1

公开(公告)日：2005-07-28

申请号：US10765531

申请日：2004-01-27

申请人： Burn Lin ,  Ping Yang ,  Hong Hsieh ,  Yao Ku ,  Chin-Hsiang Lin ,  Chiu Yoo

发明人： Burn Lin ,  Ping Yang ,  Hong Hsieh ,  Yao Ku ,  Chin-Hsiang Lin ,  Chiu Yoo

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F7/20 ,  G03F9/00 ,  H01L21/00

CPC分类号： G03F7/70425 ,  G03F1/72 ,  G03F1/76 ,  G03F1/84 ,  G03F7/70383 ,  G03F9/7003 ,  G03F9/7011 ,  G03F9/7046 ,  G03F9/7049

摘要： A method and system is disclosed for processing one or more oblique features on a mask or reticle substrate. After aligning the mask or reticle substrate with a predetermined reference system, an offset angle of a feature to be processed on the mask or reticle substrate with regard to either the horizontal or vertical reference direction of the predetermined reference system is determined. The mask or reticle substrate is rotated in a predetermined direction by the offset angle; and the feature on the mask or reticle substrate is processed using the predetermined reference system wherein the feature is processed in either the horizontal or vertical reference direction thereof.

摘要翻译： 公开了一种用于处理掩模或掩模版基板上的一个或多个倾斜特征的方法和系统。 在掩模或掩模版基板与预定的参考系统对准之后，确定相对于预定参考系的水平或垂直参考方向在掩模或掩模版基板上要处理的特征的偏移角。 掩模或掩模版基板沿预定方向旋转偏移角; 并且使用预定的参考系统处理掩模或掩模版基板上的特征，其中特征在水平或垂直参考方向上被处理。

公开(公告)号：US20050003668A1

公开(公告)日：2005-01-06

申请号：US10837528

申请日：2004-04-30

申请人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

发明人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76224

摘要： The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

摘要翻译： 本发明涉及半导体器件的处理方法。 使用等离子体气相沉积工艺来填充具有氧化物层的沟槽，其中通过氧化物层形成尖角。 进行预平面化溅射工艺以减少氧化物层拐角锐度。 使用抛光进行平坦化处理。

公开(公告)号：US09976215B2

公开(公告)日：2018-05-22

申请号：US13460884

申请日：2012-05-01

申请人： You-Hua Chou ,  Chih-Tsung Lee ,  Shu-Fen Wu ,  Chin-Hsiang Lin

发明人： You-Hua Chou ,  Chih-Tsung Lee ,  Shu-Fen Wu ,  Chin-Hsiang Lin

IPC分类号： C23C16/455 ,  C23C16/509

CPC分类号： C23C16/45565 ,  C23C16/5096

摘要： An apparatus and method are disclosed for forming thin films on a semiconductor substrate. The apparatus in one embodiment includes a process chamber configured for supporting the substrate, a gas excitation power source, and first and second gas distribution showerheads fluidly coupled to a reactive process gas supply containing film precursors. The showerheads dispense the gas into two different zones above the substrate, which is excited to generate an inner plasma field and an outer plasma field over the wafer. The apparatus deposits a material on the substrate in a manner that promotes the formation of a film having a substantially uniform thickness across the substrate. In one embodiment, the substrate is a wafer. Various embodiments include first and second independently controllable power sources connected to the first and second showerheads to vary the power level and plasma intensity in each zone.

公开(公告)号：US09727049B2

公开(公告)日：2017-08-08

申请号：US13603079

申请日：2012-09-04

申请人： Chia-Tong Ho ,  Po-Feng Tsai ,  Jung-Chang Chen ,  Tze-Liang Lee ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Chia-Tong Ho ,  Po-Feng Tsai ,  Jung-Chang Chen ,  Tze-Liang Lee ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  G05B19/4065

CPC分类号： G05B19/4065 ,  G05B2219/37252 ,  G05B2219/45031

摘要： The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.

公开(公告)号：US09054194B2

公开(公告)日：2015-06-09

申请号：US12652947

申请日：2010-01-06

申请人： Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

发明人： Chih-Hang Tung ,  Chin-Hsiang Lin ,  Cheng-Hung Chang ,  Sey-Ping Sun

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L29/41791 ,  H01L29/66803 ,  H01L29/7839 ,  H01L29/785 ,  H01L2029/7858

摘要： Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.

摘要翻译： 描述了非平面晶体管及其制造方法。 在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。 在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。 掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

公开(公告)号：US09000798B2

公开(公告)日：2015-04-07

申请号：US13495421

申请日：2012-06-13

申请人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G01R31/02 ,  G01R31/28 ,  H01L23/544

CPC分类号： G01R1/07364 ,  G01R1/06705 ,  G01R31/2887 ,  G01R31/2891 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/00 ,  H01L2924/0002

摘要： A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

摘要翻译： 公开了一种用于将诸如晶片级测试探针的探针与晶片接触件对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。

公开(公告)号：US08944739B2

公开(公告)日：2015-02-03

申请号：US13486024

申请日：2012-06-01

申请人： Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

发明人： Shih-Hung Chen ,  Ying Xiao ,  Chin-Hsiang Lin

IPC分类号： H01L21/677

CPC分类号： H01L21/6773 ,  H01L21/67733 ,  H01L21/67775

摘要： A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.

摘要翻译： 一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。 在一个实施例中，该装置是装载端口机构，其包括具有第一和第二安装端的外壳，每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合，以及至少一个可运输的晶片传送机械手 在对接端口之间的晶片。 晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。 桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输，而不依赖于FAB的自动化材料处理系统（AMHS），用于在诸如FOUP或其它晶片载体之间的体晶片传输。

公开(公告)号：US08848163B2

公开(公告)日：2014-09-30

申请号：US13050251

申请日：2011-03-17

申请人： Hsien-Cheng Wang ,  Chin-Hsiang Lin ,  Heng-Jen Lee ,  Ching-Yu Chang ,  Hua-Tai Lin ,  Burn Jeng Lin

发明人： Hsien-Cheng Wang ,  Chin-Hsiang Lin ,  Heng-Jen Lee ,  Ching-Yu Chang ,  Hua-Tai Lin ,  Burn Jeng Lin

IPC分类号： G03B27/52 ,  G03B27/42

CPC分类号： G03F7/0397 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/30 ,  G03F7/38 ,  G03F7/70858 ,  Y10S430/106 ,  Y10S430/111

摘要： A lithography apparatus generates a tunable magnetic field to facilitate processing of photoresist. The lithography apparatus includes a chamber and a substrate stage in the chamber operable to hold a substrate. A magnetic module provides a magnetic field to the substrate on the substrate stage. The magnetic module is configured to provide the magnetic field in a tunable and alternating configuration with respect to its magnitude and frequency. The magnetic field is provided to have a gradient in magnitude along a Z-axis that is perpendicular to the substrate stage to cause magnetically-charged particles disposed over the substrate stage to move up and down along the Z-axis. The lithography apparatus also includes a radiation energy source and an objective lens configured to receive radiation energy from the radiation energy source and direct the radiation energy toward the substrate positioned on the substrate stage.

摘要翻译： 光刻设备产生可调磁场以便于光致抗蚀剂的加工。 光刻设备包括腔室和腔室中的衬底台，其可操作以保持衬底。 磁性模块为衬底台上的衬底提供磁场。 磁模块被配置为相对于其幅度和频率提供可调和交替配置的磁场。 磁场被提供为具有沿垂直于衬底台的Z轴的幅度梯度，以使得设置在衬底台上的带磁性颗粒沿Z轴上下移动。 光刻设备还包括辐射能量源和物镜，其被配置为从辐射能量源接收辐射能量并将辐射能量引向位于衬底台上的衬底。