公开(公告)号：US07348211B2

公开(公告)日：2008-03-25

申请号：US11117158

申请日：2005-04-27

申请人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Ying-Ren Lin ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

摘要翻译： 提出了制造半导体封装的方法。 制备各自具有芯片的多个基板。 每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。 制备具有多个开口的载体。 每个开口的长度和宽度大于衬底。 基板定位在相应的开口中，基板和载体之间的间隙被密封。 执行成型工艺以在每个开口上形成密封剂以封装芯片。 由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。 在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。 避免了衬底材料的浪费。

公开(公告)号：US20080032450A1

公开(公告)日：2008-02-07

申请号：US11904744

申请日：2007-09-27

申请人： Chien-Ping Huang

发明人： Chien-Ping Huang

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A chip-stacked semiconductor package and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers, and a heat sink module plate including a plurality of heat sinks are provided, wherein a plurality of through holes are formed around each of the heat sinks. First chips, the heat sink module plate, and second chips are successively stacked on the chip carrier module plate, wherein the second chips are electrically connected to the chip carrier module plate by conductive wires penetrating the through holes of the heat sink module plate. After a molding process is completed, a singulation process can be performed to separate the chip carriers and the heat sinks, and thus individual semiconductor packages for integrating the heat sinks with the stacked chips are fabricated.

摘要翻译： 提出了一种芯片堆叠半导体封装及其制造方法。 提供了包括多个芯片载体的芯片载体模块板和包括多个散热片的散热模块板，其中在每个散热器周围形成有多个通孔。 第一芯片，散热器模块板和第二芯片依次堆叠在芯片载体模块板上，其中第二芯片通过穿过散热器模块板的通孔的导线与芯片载体模块板电连接。 在完成模制工艺之后，可以进行单片化处理以分离芯片载体和散热器，并且因此制造用于将散热器与堆叠芯片集成的单个半导体封装。

公开(公告)号：US20070243666A1

公开(公告)日：2007-10-18

申请号：US11725512

申请日：2007-03-19

申请人： Chien-Ping Huang ,  Chien-Chih Chen ,  Yu-Chieh Tsai

发明人： Chien-Ping Huang ,  Chien-Chih Chen ,  Yu-Chieh Tsai

IPC分类号： H01L21/00

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/0259 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/284 ,  H05K2201/09063 ,  H05K2201/0909 ,  H01L2224/85 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package, an array arranged substrate structure for the semiconductor package, and fabrication method of the semiconductor package are disclosed. First, a substrate having a plurality of array arranged substrate units is provided, and electroplating buses are formed between the substrate units. Each substrate unit has a plurality of electrically connecting pads and a plurality of conductive traces for connecting the electrically connecting pads to the electroplating buses such that an electroplating metallic layer can be formed on the electrically connecting pads via the electroplating buses and the conductive traces. Then, slots are further formed between the substrate units for disconnecting connections between the conductive traces and the electroplating buses, thus, enable each of the substrate units to become electrically independent from each other for a pre-proceeding electrical O/S test. Moreover, the slots are filled with a filling material such as an insulating gel or an encapsulant during a Molding process. Further, a cutting process is performed between the substrate units through the filling material or encapsulant filling the slots upon completion of encapsulation. Thus, the cutting surface can be kept smooth and exposure of conductive traces from the cutting surface is avoided, thereby preventing static electricity and humidity from adversely affecting the product quality.

摘要翻译： 公开了半导体封装，用于半导体封装的阵列布置衬底结构以及半导体封装的制造方法。 首先，提供具有多个阵列排列的基板单元的基板，并且在基板单元之间形成电镀总线。 每个基板单元具有多个电连接焊盘和用于将电连接焊盘连接到电镀总线的多个导电迹线，使得可以经由电镀母线和导电迹线在电连接焊盘上形成电镀金属层。 然后，在衬底单元之间进一步形成槽，用于断开导电迹线和电镀母线之间的连接，从而使每个衬底单元彼此电独立以进行预处理电气O / S测试。 此外，在成型过程中，槽中填充诸如绝缘凝胶或密封剂的填充材料。 此外，在完成封装之后，通过填充材料或填充槽的密封剂在衬底单元之间进行切割处理。 因此，切割面可以保持平滑，并且避免了来自切割表面的导电迹线的暴露，从而防止静电和湿气对产品质量产生不利影响。

公开(公告)号：US07274088B2

公开(公告)日：2007-09-25

申请号：US10196305

申请日：2002-07-16

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L29/40

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US20070164403A1

公开(公告)日：2007-07-19

申请号：US11633876

申请日：2006-12-04

申请人： Chien-Ping Huang ,  Chin-Huang Chang

发明人： Chien-Ping Huang ,  Chin-Huang Chang

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure and a fabrication method thereof are provided. A semiconductor chip having an active surface and an inactive surface is coupled to a substrate. A plurality of bond pads are formed on the active surface of the semiconductor chip. The substrate can be arranged to expose the bond pads. The semiconductor chip is further attached to a lead frame having a plurality of leads, each of which has an inner portion and an outer portion higher than the inner portion, such that the semiconductor chip can be accommodated in the inner portions of the leads. An encapsulant is formed to cover the semiconductor chip and the substrate, and bottom surfaces of the leads of the lead frame are exposed from the encapsulant, so as to form a thin and compact package structure, which can package various semiconductor chips having different arrangements of bond pads.

摘要翻译： 提供半导体封装结构及其制造方法。 具有活性表面和非活性表面的半导体芯片被耦合到基板。 在半导体芯片的有源表面上形成多个接合焊盘。 衬底可以布置成暴露接合焊盘。 半导体芯片还附着在具有多个引线的引线框架上，每个引线具有内部部分和高于内部部分的外部部分，使得半导体芯片可以容纳在引线的内部。 形成密封剂以覆盖半导体芯片和基板，并且引线框架的引线的底表面从密封剂暴露，以形成薄且紧凑的封装结构，其可以封装具有不同布置的各种半导体芯片 接合垫

公开(公告)号：US07242068B2

公开(公告)日：2007-07-10

申请号：US10953915

申请日：2004-09-28

申请人： Chien-Ping Huang

发明人： Chien-Ping Huang

IPC分类号： H01L31/0203 ,  H01L23/495

CPC分类号： H01L31/0203 ,  H01L23/49861 ,  H01L27/14618 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.

摘要翻译： 提出了一种光敏半导体封装及其制造方法及其引线框架。 引线框架具有管芯焊盘和多个引线，其中至少一个凹部形成在靠近管芯焊盘的每个引线的端部处，并且至少一个凹陷区域形成在管芯焊盘上。 密封剂填充凹陷部分，凹陷区域以及引线和芯片焊盘之间，并且形成在引线框架上以限定芯片接收腔。 感光芯片安装在芯片接收腔中，其中至少部分地将芯片的非活性表面附着到填充凹陷区域并且不与凹陷区域接触的密封剂。 可透光单元连接到形成在引线框架上的密封剂以密封芯片接收腔。

公开(公告)号：US20070075423A1

公开(公告)日：2007-04-05

申请号：US11295885

申请日：2005-12-06

申请人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor element with conductive bumps and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor element having a plurality of bond pads formed on an active surface thereof, wherein each of the bond pads has a predetermined bonding area; applying a passivation layer on the active surface, with a plurality of openings formed for exposing the predetermined bonding areas; applying a buffer layer on the passivation layer to cover the predetermined bonding areas; allowing the buffer layer with a plurality of openings to be formed for exposing a portion of the predetermined bonding areas; forming a under bump metallurgy (UBM) layer on the bond pads, allowing the predetermined bonding areas to be completely covered by the UBM layer; and implanting conductive bumps on the UBM layer. The buffer layer advantageously absorbs stresses exerted to the conductive bumps, thereby preventing the conducting bumps from cracking.

摘要翻译： 提供具有导电凸块的半导体元件及其制造方法。 该制造方法包括提供在其活性表面上形成有多个接合焊盘的半导体元件，其中每个接合焊盘具有预定的接合面积; 在活性表面上施加钝化层，其中形成有用于暴露预定粘合区域的多个开口; 在所述钝化层上施加缓冲层以覆盖所述预定的接合区域; 允许形成具有多个开口的缓冲层以暴露预定粘合区域的一部分; 在所述接合焊盘上形成凹凸不平的冶金（UBM）层，允许所述预定接合区域被所述UBM层完全覆盖; 并在UBM层上注入导电凸块。 缓冲层有利地吸收施加到导电凸块的应力，从而防止导电凸起破裂。

公开(公告)号：US20070059865A1

公开(公告)日：2007-03-15

申请号：US11164322

申请日：2005-11-18

申请人： Chien-Ping Huang ,  Fu-Di Tang

发明人： Chien-Ping Huang ,  Fu-Di Tang

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

摘要翻译： 提供了具有支撑结构的半导体封装及其制造方法。 通过将芯片电连接到形成在载体上的电触头，进行成型工艺。 形成在载体上的多个凹部填充有用于在模制过程中封装芯片的密封剂。 在移除载体之后，填充凹部的密封剂的一部分在密封剂的表面上形成向外突出的部分，使得半导体封装可以经由突出部分附接到外部装置。

公开(公告)号：US20070034998A1

公开(公告)日：2007-02-15

申请号：US11580560

申请日：2006-10-12

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。

公开(公告)号：US20060292741A1

公开(公告)日：2006-12-28

申请号：US11471516

申请日：2006-06-21

申请人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

发明人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.

摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装并电连接到基板。 散热结构包括散热器和至少一个支撑部分，其中支撑部分在用于半导体封装的预定封装区域外的位置处附接到基板，并且半导体芯片设置在散热器下方。 在基板上形成密封剂以封装半导体芯片和散热结构，其中密封剂在基板上的投影面积大于预定封装面积。 沿着预定包装区域的边缘进行切割处理以去除位于预定包装区域外部的密封剂，支撑部分和基底的部分，以形成与散热结构集成的半导体封装。