公开(公告)号：US08703557B1

公开(公告)日：2014-04-22

申请号：US13863044

申请日：2013-04-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/6681 ,  H01L21/823821

Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.

Abstract translation: 本文公开的一种方法包括在限定多个翅片的基底中形成多个翅片形成沟槽，其中至少一个翅片是虚拟翅片，形成填充沟槽的至少一部分的绝缘材料，形成 在绝缘材料上形成的掩模层中的凹槽，在凹槽的侧壁上形成侧壁间隔物，以限定间隔开口，通过间隔开口在掩模层上执行至少一个第一蚀刻工艺，以在 暴露绝缘材料和虚拟鳍片的一部分的掩模层，并且执行至少一个第二蚀刻工艺以去除所述虚拟鳍片的至少一部分，从而限定所述绝缘材料中的开口。

公开(公告)号：US20140042502A1

公开(公告)日：2014-02-13

申请号：US13957587

申请日：2013-08-02

Applicant: Globalfoundries Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

公开(公告)号：US20190148557A1

公开(公告)日：2019-05-16

申请号：US16242834

申请日：2019-01-08

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L21/321 ,  H01L21/02

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

公开(公告)号：US20180277648A1

公开(公告)日：2018-09-27

申请号：US15986031

申请日：2018-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/20 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/10

Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US09892926B2

公开(公告)日：2018-02-13

申请号：US15462657

申请日：2017-03-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/7856 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/3212 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/78654

Abstract: Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.

公开(公告)号：US09793341B1

公开(公告)日：2017-10-17

申请号：US15170224

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Davood Shahrjerdi ,  Herbert L. Ho ,  Kangguo Cheng

IPC: H01L27/108 ,  H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/92

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a deep trench capacitor, integrated structures and methods of manufacture. The structure includes: a conductive material formed on an underside of an insulator layer and which acts as a back plate of a deep trench capacitor; an inner conductive layer extending through the insulator layer and an overlying substrate; and a dielectric liner between the inner conductive material and the conductive material, and formed on a sidewall of an opening within the insulator layer and the overlying substrate.

公开(公告)号：US20170117276A1

公开(公告)日：2017-04-27

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L21/2018 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.

公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

公开(公告)号：US09633906B2

公开(公告)日：2017-04-25

申请号：US14162904

申请日：2014-01-24

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US09589848B2

公开(公告)日：2017-03-07

申请号：US14678024

申请日：2015-04-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Ghavam G. Shahidi

IPC: H01L21/027 ,  H01L21/205 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/20 ,  H01L21/033 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L21/3065 ,  H01L29/16

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract translation: 在半导体晶片或其它基板上形成硅和硅锗翅片，以便于产生紧密间隔的nFET和pFET器件。 在形成填充凹部的硅锗层的外延生长之前，使用图案化心轴层在晶片中形成一个或多个凹槽。 间隔件形成在图案化心轴层的侧壁上，随后移除心轴层。 蚀刻在间隔物之间​​的晶片和硅锗层的暴露区域以形成可用于来自晶片的nFET器件的鳍片和可用于来自硅锗层的pFET器件的鳍片。