公开(公告)号：US10305019B1

公开(公告)日：2019-05-28

申请号：US14229820

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff

IPC: H01L41/09 ,  H01L41/23 ,  H01L41/047 ,  H01L41/053

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

公开(公告)号：US10291283B2

公开(公告)日：2019-05-14

申请号：US15088996

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Feras Eid ,  Adel A. Elsherbini ,  Georgios C. Dogiamis ,  Vijay K. Nair ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H04B1/48 ,  H03H7/38 ,  H01H57/00 ,  H03H15/00

Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.

公开(公告)号：US20190096798A1

公开(公告)日：2019-03-28

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/40 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US20190038170A1

公开(公告)日：2019-02-07

申请号：US15837508

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Amit Baxi ,  Adel Elsherbini ,  Vincent Mageshkumar ,  Sasha Oster ,  Aleksandar Aleksov ,  Feras Eid

IPC: A61B5/0408 ,  A61B5/01 ,  A61B5/026 ,  A61B5/00 ,  A61B5/0205

Abstract: Sensing patch systems are disclosed herein. A sensing patch system includes a flexible substrate and a sensor node. The flexible substrate includes one or more substrate sensors configured to provide sensor data, one or more substrate conductors electrically coupled to a corresponding substrate sensor to conduct the sensor data provided by the corresponding substrate sensor, and a node interface. The sensor node includes a substrate interface configured to receive the node interface of the flexible substrate. The sensor node is configured to receive the sensor data provided by the substrate sensors, process the sensor data, and communicate the processed sensor data to a remote device.

公开(公告)号：US20180263117A1

公开(公告)日：2018-09-13

申请号：US15810800

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravindranath V. Mahajan ,  James C. Matayabas, JR. ,  Johanna M. Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US20180164580A1

公开(公告)日：2018-06-14

申请号：US15376414

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Ginni Grover ,  Sasha N. Oster ,  Feras Eid ,  Seth E. Hunter

IPC: G02B26/08 ,  C23C30/00

CPC classification number: G02B26/0833 ,  C23C30/00 ,  G02B17/002

Abstract: Embodiments include techniques and configurations for apparatuses and methods for making an optical imaging device based on a micro mirror array. The method may include forming an array of trenches in a substrate. The array of trenches may be formed by intersecting a first plurality of walls with a second plurality of walls in the substrate. A trench of the array of trenches may be formed by adjacent walls of the first plurality of walls and intersecting adjacent walls of the second plurality of walls. A wall of the trench may include a side surface coupled with a top surface. A reflective layer may be deposited conformally to cover the side surface of the wall and to serve as a reflector. A supporting layer may be formed above the substrate, or within the array of trenches, to provide mechanical support for the array of trenches. Other embodiments may be claimed.

公开(公告)号：US20180020982A1

公开(公告)日：2018-01-25

申请号：US15215529

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Aleksandar Aleksov ,  Sasha N. Oster ,  Amit Sudhir Baxi ,  Feras Eid ,  Johanna M. Swan ,  Vincent S. Mageshkumar

IPC: A61B5/00 ,  A61B5/0205 ,  A61B5/1455 ,  A61B5/0408

CPC classification number: A61B5/6833 ,  A61B5/0205 ,  A61B5/024 ,  A61B5/04087 ,  A61B5/08 ,  A61B5/14551 ,  A61B5/7271 ,  A61B5/7405 ,  A61B5/742 ,  A61B5/7455 ,  A61B5/746 ,  A61B2560/0204 ,  A61B2560/0412 ,  A61B2560/0443

Abstract: Discussed generally herein are methods and devices including or providing a wellness monitoring system. The wellness monitoring system can include a first patch including a flexible, stretchable first substrate, a first adhesive on the first substrate, the first adhesive configured to attach the first patch to skin of a user, and first electronics on or at least partially in the first substrate, the first electronics to monitor a first biological parameter of the user, and a second patch including a flexible, stretchable second substrate, a second adhesive on the second substrate, the second adhesive configured to attach the second patch to skin of the user, and second electronics on or at least partially in the second substrate, the second electronics to monitor a second biological parameter of the user, the second biological parameter different from the first biological parameter.

公开(公告)号：US09865941B1

公开(公告)日：2018-01-09

申请号：US15281814

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Adel A. Elsherbini ,  Feras Eid ,  Aleksandar Aleksov ,  Amit Sudhir Baxi ,  Johanna M. Swan ,  Vincent S. Mageshkumar

IPC: A61B17/00 ,  H01R4/58 ,  H01R43/26 ,  H01R13/03 ,  A44B17/00 ,  A44B19/24

CPC classification number: H01R4/58 ,  A44B17/0041 ,  A44B19/24 ,  H01R13/03 ,  H01R43/26

Abstract: A system can include a first portion of a fabric fastener, a second portion of the fabric fastener, wherein the first portion and the second portion are configured to mechanically connect with each other and to resist separation from each other once connected, and wherein the first and second portions include a plurality of corresponding electrical contacts configured to form a plurality of individual electrical connections when the first portion is mechanically connected with the second portion.

公开(公告)号：US09800015B2

公开(公告)日：2017-10-24

申请号：US15056794

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC: H01L27/15 ,  H01L31/12 ,  H01S5/022 ,  H01L23/00 ,  H01L25/16 ,  H01S5/183

CPC classification number: H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

公开(公告)号：US09735893B1

公开(公告)日：2017-08-15

申请号：US15216502

申请日：2016-07-21

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sasha N. Oster ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Kumar Ranganathan ,  Wen-Ling M. Huang

IPC: A61B5/11 ,  A61B5/01 ,  A61B5/00 ,  A61B5/0402 ,  A61B5/021 ,  A61N1/04 ,  A61M5/142 ,  A61B5/145 ,  H04B5/00 ,  H04B13/00 ,  A61N7/00

CPC classification number: H04B13/005 ,  A61B5/0024 ,  A61B5/01 ,  A61B5/0205 ,  A61B5/021 ,  A61B5/0402 ,  A61B5/0432 ,  A61B5/1102 ,  A61B5/1107 ,  A61B5/1121 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/4839 ,  A61B5/4869 ,  A61B5/6833 ,  A61F7/007 ,  A61M5/14248 ,  A61N1/0484 ,  A61N1/0492 ,  A61N1/3603 ,  A61N7/00 ,  H04B5/0012

Abstract: Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy to a user. A body-area network can include a plurality of communicatively coupled patches that communicate with an intermediate device. The intermediate device can provide data representative of a biological parameter monitored by the patches to proper personnel, such as for diagnosis and/or response.