公开(公告)号：US20190121422A1

公开(公告)日：2019-04-25

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/084 ,  G06F12/0802 ,  G06F1/28 ,  G06F12/0864 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190011976A1

公开(公告)日：2019-01-10

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US10067553B2

公开(公告)日：2018-09-04

申请号：US15270208

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/08 ,  G06F1/32 ,  G06F12/084 ,  G06F12/0864 ,  G06F1/28 ,  G06F12/0802 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US10007528B2

公开(公告)日：2018-06-26

申请号：US13683748

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann ,  Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas ,  Neelam Chandwani ,  Michael A. Rothman ,  Robert Gough ,  Mark Doran

IPC: G06F17/30 ,  G06F9/4401 ,  G06F9/44 ,  G06F9/445 ,  G06F1/28 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/30 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F16/2282 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US09983644B2

公开(公告)日：2018-05-29

申请号：US14936945

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shmuel Zobel ,  Maxim Levit ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

公开(公告)号：US20180120924A1

公开(公告)日：2018-05-03

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20180060123A1

公开(公告)日：2018-03-01

申请号：US15252511

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Israel Hirsh ,  Efraim Rotem ,  Doron Rajwan ,  Avinash N. Ananthakrishnan ,  Natanel Abitan ,  Ido Melamed ,  Guy M. Therien

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F1/32 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5094 ,  Y02D10/24

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

公开(公告)号：US20180004269A1

公开(公告)日：2018-01-04

申请号：US15197083

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Alexander Gendler ,  Ankush Varma

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/325 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/44 ,  Y02D10/126 ,  Y02D10/152

Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.

公开(公告)号：US09684541B2

公开(公告)日：2017-06-20

申请号：US14319099

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Arik Gihon ,  Efraim Rotem ,  Paul S. Diefenbaugh ,  Eric C. Samson ,  Michael Mishaeli ,  Yoni Aizik ,  Chen Ranel

IPC: G06T15/00 ,  G06F9/50 ,  G06F3/14

CPC classification number: G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

公开(公告)号：US20170131754A1

公开(公告)日：2017-05-11

申请号：US14936945

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shmuel Zobel ,  Maxim Levit ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.