公开(公告)号：US09570145B2

公开(公告)日：2017-02-14

申请号：US14554904

申请日：2014-11-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/14

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

Abstract translation: 本实施例提供一种支持存储设备中的自刷新操作的系统。 在操作期间，系统将存储器设备从自动刷新状态转变，其中存储器控制器将存储器设备的刷新操作控制到自刷新状态，其中存储器设备控制刷新操作。 当存储器件处于自刷新状态时，系统将刷新操作的进程信息从存储器件发送到存储器控制器。 接下来，当从自刷新状态返回到自动刷新状态时，系统使用从存储装置接收到的进度信息来控制存储器控制器的后续操作的顺序。

公开(公告)号：US09569308B1

公开(公告)日：2017-02-14

申请号：US14328941

申请日：2014-07-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1048 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/356 ,  H03M13/6502

Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

Abstract translation: 存储器控制器可操作在误差检测/校正模式中，其中N个校正子值分别应用于数据量的N个数据字，但是单个奇偶校验位在数据量的所有N个数据字上被共享。

公开(公告)号：US09563597B2

公开(公告)日：2017-02-07

申请号：US14386561

申请日：2012-12-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C5/02 ,  G11C29/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。

公开(公告)号：US09502096B2

公开(公告)日：2016-11-22

申请号：US14573323

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/32 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20160328008A1

公开(公告)日：2016-11-10

申请号：US15214266

申请日：2016-07-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract translation: 动态地改变设备之间的信息传输的带宽以适应系统中使用的功率模式之间的转换。 通过选择性地启用和禁用携带信息的各个控制链路和数据链路来改变带宽。 在系统的最高带宽模式下，所有的数据和控制链路都可以在整个过程中提供最大的信息。 在系统的一个或多个较低带宽模式期间，禁用至少一个数据链路和/或至少一个控制链路以减少设备的功耗。 在每个低带宽模式期间，至少一个数据链路和至少一个控制链路保持使能。 对于这些链路，相同的信令速率用于两种带宽模式，以减少由信号速率变化引起的延迟。 此外，为禁用的链接生成校准信息，以便这些链接可以快速恢复使用。

公开(公告)号：US09490009B2

公开(公告)日：2016-11-08

申请号：US14987309

申请日：2016-01-04

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract translation: 存储单元包括第一电阻性存储器元件，在公共节点处与第一电阻式存储器元件电耦合的第二电阻存储元件，以及包括与公共节点电耦合的输入端的开关元件，该开关元件包括驱动器配置 在一个或多个操作期间浮动。

公开(公告)号：US20160307609A1

公开(公告)日：2016-10-20

申请号：US15138424

申请日：2016-04-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20160293239A1

公开(公告)日：2016-10-06

申请号：US15090399

申请日：2016-04-04

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G11C8/08 ,  G11C29/44 ,  G06F11/07 ,  G11C8/06

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract translation: 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。

公开(公告)号：US20160275033A1

公开(公告)日：2016-09-22

申请号：US15169275

申请日：2016-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F13/40 ,  G11C5/02 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/00 ,  G06F12/02 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/4282 ,  G11C5/02

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Abstract translation: 多芯片封装包括形成有多个存储器控制器电路的逻辑集成电路（IC）管芯，第一存储器IC管芯和第二存储器IC管芯。 第二存储器IC管芯安装到第一存储器IC管芯。 第一存储器IC管芯和逻辑IC管芯彼此安装。 逻辑IC芯片包括用于耦合到多个串行链路的串行链路接口。 第一存储器管芯包括由多个存储器控制器电路中的第一个访问的第一存储器组和由多个存储器控制器电路中的第二存储器控制器电路访问的第二存储器组。

公开(公告)号：US20160260469A1

公开(公告)日：2016-09-08

申请号：US15155794

申请日：2016-05-16

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4072

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.