公开(公告)号：US20160190323A1

公开(公告)日：2016-06-30

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US09368591B2

公开(公告)日：2016-06-14

申请号：US14334950

申请日：2014-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

IPC: H01L21/338 ,  H01L29/45

CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

公开(公告)号：US20160163863A1

公开(公告)日：2016-06-09

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/201 ,  H01L21/02 ,  H01L29/161 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。

公开(公告)号：US09362405B1

公开(公告)日：2016-06-07

申请号：US14560361

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括在翅片的整个轴向长度周围围绕翅片的暴露部分形成初始外延半导体包层材料，在其周围形成牺牲栅极结构 去除所述牺牲栅极结构从而限定替换栅极腔，通过所述替换栅极腔执行蚀刻工艺以移除所述初始包层材料的至少暴露部分，从而暴露出所述牺牲栅极结构 在替换栅极腔内的翅片的表面，在散热片的暴露表面周围形成至少一个替代外延半导体覆层材料，以及在所述替代栅极腔内形成围绕所述至少一个替代外延半导体包层材料的替代栅极结构。

公开(公告)号：US09349658B1

公开(公告)日：2016-05-24

申请号：US14608625

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.

Abstract translation: 一个说明性实施例涉及在衬底中形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一氧化阻挡层，以便覆盖下部分的侧壁的一部分但不是全部 在绝缘材料的第一氧化阻挡层之上形成第二绝缘材料层，并进行热退火处理以将位于第一氧化阻挡层之上的翅片的下部的部分转化而不是全部 绝缘材料层形成位于翅片下方的氧化物鳍片隔离区域。

公开(公告)号：US20160133692A1

公开(公告)日：2016-05-12

申请号：US14982474

申请日：2015-12-29

Applicant: STMicroelectronics, Inc. ,  Commissariat a I'energie Atomique et Aux Energies Alternatives ,  GlobalFoundries Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract translation: 描述了从双轴应变半导体层形成单轴应变纳米级半导体条的方法和结构。 可以使用空间双倍的心轴工艺来形成用于图案化通过双轴应变半导体层的致密的窄沟槽的掩模。 所得到的双轴应变层的切片增强了载流子迁移率并且可以提高器件性能。

公开(公告)号：US20160093713A1

公开(公告)日：2016-03-31

申请号：US14963378

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

Abstract translation: 晶体管器件包括半导体衬底和位于半导体衬底表面之上的栅极结构。 栅极结构包括位于半导体衬底的表面上方的高k栅极绝缘层和位于高k栅极绝缘层上方的材料的至少一个功函数调节层，其中该至少一个工件的上表面 当在晶体管器件的栅极宽度方向上截取的横截面中观察时，材料的功能调节层具有阶梯形轮廓。 栅极结构还包括位于至少一个功函数调节层材料的阶梯状上表面上的导电材料层。

公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract translation: 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。

公开(公告)号：US09263580B2

公开(公告)日：2016-02-16

申请号：US14223373

申请日：2014-03-24

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。

公开(公告)号：US09224605B2

公开(公告)日：2015-12-29

申请号：US14267154

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Shurong Liang

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/165 ,  H01L29/167 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/324 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6681 ,  H01L29/7849

Abstract: One method disclosed includes removing at least a portion of a fin to thereby define a fin trench in a layer of insulating material, forming a substantially defect-free first layer of semiconductor material in the fin trench, forming a second layer of semiconductor material on an as-formed upper surface of the first layer of semiconductor material, forming an implant region at the interface between the first layer of semiconductor material and the substrate, performing an anneal process to induce defect formation in at least the first layer of semiconductor material, forming a third layer of semiconductor material on the second layer of semiconductor material, forming a layer of channel semiconductor material on the third layer of semiconductor material, and forming a gate structure around at least a portion of the channel semiconductor material.

Abstract translation: 公开的一种方法包括去除鳍片的至少一部分，从而在绝缘材料层中限定翅片沟槽，在翅片沟槽中形成基本上无缺陷的半导体材料层，在第二层半导体材料上形成第二层半导体材料 形成第一半导体材料层的上表面，在第一半导体材料层和衬底之间的界面处形成注入区域，执行退火工艺以在至少第一半导体材料层中形成缺陷，形成 在所述第二半导体材料层上的第三层半导体材料，在所述第三半导体材料层上形成沟道半导体材料层，以及围绕所述沟道半导体材料的至少一部分形成栅极结构。