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162 条记录 (耗时 0.035 秒)

    Image sensor cells
    121.
    发明授权
    Image sensor cells 有权
    图像传感器单元

    公开(公告)号：US07205627B2

    公开(公告)日：2007-04-17

    申请号：US10906510

    申请日：2005-02-23

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

    IPC分类号： H01L31/06

    CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

    摘要： A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.

    摘要翻译： 用于图像传感器单元的结构（及其形成方法）。 该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

    Designing scan chains with specific parameter sensitivities to identify process defects
    122.
    发明授权
    Designing scan chains with specific parameter sensitivities to identify process defects 失效
    设计具有特定参数灵敏度的扫描链，以识别过程缺陷

    公开(公告)号：US07194706B2

    公开(公告)日：2007-03-20

    申请号：US10710642

    申请日：2004-07-27

    申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

    摘要翻译： 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

    Method of controlling floating body effects in an asymmetrical SOI device
    124.
    发明授权
    Method of controlling floating body effects in an asymmetrical SOI device 有权
    控制非对称SOI器件浮体效应的方法

    公开(公告)号：US06756637B2

    公开(公告)日：2004-06-29

    申请号：US09899957

    申请日：2001-07-06

    申请人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    发明人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    IPC分类号： H01L2976

    CPC分类号： H01L29/78612 ,  H01L21/26586

    摘要： High performance asymmetric transistors including controllable diode characteristics at the source and/or drain are developed by supplying impurities with high accuracy of location by angled implants in a trench or diffusion from a solid body formed as a sidewall of doped material. High concentration gradient of impurities to support high performance is achieved by providing for reduced heat treatment after the impurity is supplied in order to limit diffusion previously necessary to achieve the desired location of impurity structures. Damascene or quasi-Damascene gate structures are also provided for high dimensional uniformity, increased manufacturing yield and structural integrity of the transistor.

    摘要翻译： 在源极和/或漏极处包括可控二极管特性的高性能不对称晶体管通过在沟槽中的倾斜注入提供高精度的杂质或从形成为掺杂材料的侧壁的固体的扩散而开发。 通过在提供杂质之后提供减少的热处理以便限制先前必需的扩散以实现杂质结构的所需位置来实现高浓度梯度的杂质以支持高性能。 还提供了大马士革或准大马士革门结构，用于高尺寸均匀性，增加的制造产量和晶体管的结构完整性。

    Device having integrated optical and copper conductors and method of fabricating same
    126.
    发明授权
    Device having integrated optical and copper conductors and method of fabricating same 失效
    具有集成光和铜导体的装置及其制造方法

    公开(公告)号：US06403393B1

    公开(公告)日：2002-06-11

    申请号：US09388163

    申请日：1999-09-01

    申请人： James W. Adkisson ,  Paul W. Pastel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Paul W. Pastel ,  Anthony K. Stamper

    IPC分类号： G02B600

    CPC分类号： G02B6/132 ,  G02B6/122 ,  G02B6/13 ,  G02B2006/121

    摘要： A method is provided for making optical waveguide structures in a semiconductor device wherein a rectangular cross-section low index of refraction material is encapsulated in a trench by a high index of refraction material. The waveguide structures may be made in a device containing copper conductors in trenches by forming new trenches to hold the optical waveguide. Copper conductor containing trenches may also be made in an electronic component containing waveguide structures and a further method is provided for forming an optical waveguide structure by replacing a copper containing trench with the waveguide structure in an electronic component having a plurality of copper containing trenches. All the methods use conventional techniques so that the fabrication of a semiconductor device containing both optical waveguide structures and copper conductor structures can be made both efficiently and economically.

    摘要翻译： 提供了一种用于在半导体器件中制造光波导结构的方法，其中通过高折射率材料将矩形横截面的低折射率材料折射率封装在沟槽中。 波导结构可以通过形成新的沟槽来保持光波导，在包含沟槽中的铜导体的器件中制成。 包含沟槽的铜导体也可以制成包含波导结构的电子部件，并且提供了另外的方法，用于通过在具有多个含铜沟槽的电子部件中用波导结构替换含铜沟槽来形成光波导结构。 所有这些方法都使用常规技术，从而可以有效地和经济地制造含有光波导结构和铜导体结构的半导体器件。

    Noise-reducing platen
    127.
    发明授权
    Noise-reducing platen 失效
    减噪压板

    公开(公告)号：US4453848A

    公开(公告)日：1984-06-12

    申请号：US381593

    申请日：1982-05-24

    申请人： James W. Adkisson ,  Paul A. Ishman

    发明人： James W. Adkisson ,  Paul A. Ishman

    IPC分类号： B41J11/053 ,  H04N1/06 ,  B41J19/04

    CPC分类号： H04N1/0692 ,  B41J11/053 ,  H04N1/06 ,  H04N2201/0446

    摘要： A noise-reducing platen comprising a circular cylinder, a hub disposed along the longitudinal axis of and within the cylinder, and walls for dividing the annular region between the cylinder and the hub into a plurality of separated longitudinal channels extending the length of the cylinder. The walls include a plurality of vanes disposed at angular intervals about the hub, each vane extending (a) from the hub to the inner surface of the cylinder and (b) along the length of the cylinder, each pair of adjacent vanes defining one of the longitudinal channels. It is believed that the vibrations generated along the longitudinal channels are at a frequency above the audible range, thereby resulting in reduced undesired noise when printing elements strike the platen.

    摘要翻译： 一种降噪压盘，包括圆柱体，沿着圆柱体的纵向轴线设置的毂，以及用于将圆柱体和轮毂之间的环形区域分隔成多个分离的纵向通道，其延伸圆柱体的长度。 壁包括围绕轮毂以角度间隔设置的多个叶片，每个叶片（a）从轮毂延伸到圆柱体的内表面，（b）沿圆柱体的长度，每对相邻的叶片限定 纵向通道。 据信，沿着纵向通道产生的振动处于高于可听范围的频率，从而当打印元件撞击压板时导致减少的不期望的噪音。

    Metal insulator metal (MIM) capacitor structure
    128.
    发明授权
    Metal insulator metal (MIM) capacitor structure 有权
    金属绝缘体金属（MIM）电容器结构

    公开(公告)号：US09252204B2

    公开(公告)日：2016-02-02

    申请号：US13233752

    申请日：2011-09-15

    申请人： James W. Adkisson ,  Panglijen Candra ,  Kevin N. Ogg ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Panglijen Candra ,  Kevin N. Ogg ,  Anthony K. Stamper

    IPC分类号： H01L49/02

    CPC分类号： H01L28/90

    摘要： A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.

    摘要翻译： MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。