公开(公告)号：USD985544S1

公开(公告)日：2023-05-09

申请号：US29697339

申请日：2019-07-08

Applicant: Jun Lu

Designer： Jun Lu

Abstract: FIG. 1 is a front side of a USB gain-adjustable microphone;
FIG. 2 is a right side view thereof;
FIG. 3 is a back view thereof;
FIG. 4 is a left side view thereof; and,
FIG. 5 is a bottom view thereof.
The broken lines depict portions of the USB gain adjustable microphone and forms no part of the claimed design.

公开(公告)号：US20200281967A1

公开(公告)日：2020-09-10

申请号：US16876592

申请日：2020-05-18

Applicant: Arne Holmgren ,  Jun Lu ,  Lili Zou

Inventor： Arne Holmgren ,  Jun Lu ,  Lili Zou

IPC: A61K33/04 ,  A61P31/04 ,  A61P31/02 ,  A61K33/38 ,  A61K9/00 ,  A61L24/00 ,  A61L24/02

Abstract: Disclosed herein are antibiotic compositions, for example compositions that comprise a metal-containing agent and an organoselenium agent, and uses thereof.

公开(公告)号：US20180185410A1

公开(公告)日：2018-07-05

申请号：US15832045

申请日：2017-12-05

Applicant: Arne Holmgren ,  Jun Lu ,  Lili Zou

Inventor： Arne Holmgren ,  Jun Lu ,  Lili Zou

IPC: A61K33/04 ,  A61L24/00 ,  A61P31/02 ,  A61L24/02 ,  A61P31/04 ,  A61K9/00

CPC classification number: A61K33/04 ,  A61K9/0014 ,  A61K9/0056 ,  A61K33/38 ,  A61L24/0015 ,  A61L24/02 ,  A61L2300/104 ,  A61L2300/406 ,  A61P31/02 ,  A61P31/04 ,  Y02A50/473 ,  A61K2300/00

Abstract: Disclosed herein are antibiotic compositions, for example compositions that comprise a metal-containing agent and an organoselenium agent, and uses thereof.

公开(公告)号：US09929076B2

公开(公告)日：2018-03-27

申请号：US13913183

申请日：2013-06-07

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/492

CPC classification number: H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

公开(公告)号：US09553316B2

公开(公告)日：2017-01-24

申请号：US14667524

申请日：2015-03-24

Applicant: Jun Lu ,  Khalil Amine ,  Larry A. Curtiss ,  Kah Chun Lau ,  Yang-Kook Sun ,  Yun Jung Lee ,  Xiangyi Luo

Inventor： Jun Lu ,  Khalil Amine ,  Larry A. Curtiss ,  Kah Chun Lau ,  Yang-Kook Sun ,  Yun Jung Lee ,  Xiangyi Luo

IPC: H01M4/90 ,  H01M4/92

CPC classification number: H01M4/9016 ,  H01M4/382 ,  H01M4/9041 ,  H01M4/92 ,  H01M4/923 ,  H01M12/08 ,  H01M2300/0028 ,  Y02E60/128

Abstract: A composition includes LiO2, reduced graphene oxide, and a metal catalyst or residue thereof.

Abstract translation: 组合物包括LiO 2，还原性氧化石墨烯，以及金属催化剂或其残余物。

公开(公告)号：US09538976B2

公开(公告)日：2017-01-10

申请号：US14131896

申请日：2012-07-27

Applicant: Paul J. Keall ,  Ricky O'Brien ,  Benjamin J. Cooper ,  Jun Lu ,  Jeffrey F. Williamson

Inventor： Paul J. Keall ,  Ricky O'Brien ,  Benjamin J. Cooper ,  Jun Lu ,  Jeffrey F. Williamson

IPC: A61B6/03 ,  A61B6/00 ,  A61N5/10

CPC classification number: A61B6/541 ,  A61B6/4085 ,  A61B6/486 ,  A61B6/5205 ,  A61B6/5264 ,  A61B6/583 ,  A61N2005/1061

Abstract: A method of optimizing 4D cone beam computed tomography (4DCBCT) imaging is provided that includes using a scanner to generate projections of a target, where the projections are used to form a cone beam computed tomography (CBCT) scan of the target, where the CBCT includes a 3D image of the target, and using an appropriately programmed computer to control rotation speed of a gantry and projection acquisition of the CBCT in real-time according to a measured patient respiratory signal, where the real-time acquisition of the 4CBCT forms an optimized 4DCBCT image set.

Abstract translation: 提供了一种优化4D锥形束计算机断层摄影（4DCBCT）成像的方法，其包括使用扫描仪产生靶的投影，其中投影用于形成目标的锥束计算机断层摄影（CBCT）扫描，其中CBCT 包括目标的3D图像，并且使用适当编程的计算机根据所测量的患者呼吸信号实时地控制台架的转速和CBCT的投影采集，其中4CBCT的实时采集形成 优化的4DCBCT图像集。

公开(公告)号：US20160104661A9

公开(公告)日：2016-04-14

申请号：US13913183

申请日：2013-06-07

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

公开(公告)号：US09214419B2

公开(公告)日：2015-12-15

申请号：US14194502

申请日：2014-02-28

Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

IPC: H01L21/44 ,  H01L23/495 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

Abstract translation: 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

公开(公告)号：US09087828B2

公开(公告)日：2015-07-21

申请号：US13797440

申请日：2013-03-12

Applicant: Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

Inventor： Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu ,  Ming-Chen Lu ,  Yan Huo ,  Aihua Lu

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/495 ,  H01L21/58 ,  H01L23/00 ,  H01L23/433 ,  H01L23/492

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L21/566 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/03

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract translation: 具有厚底部金属的半导体器件包括在其前表面覆盖有顶部塑料封装层的半导体芯片和在其后表面处的背面金属层，顶部塑料封装层围绕金属凸块的侧壁与金属的顶表面 从顶部塑料封装层暴露的凸起，用于半导体芯片的芯片安装在其上以及塑料封装主体。

公开(公告)号：US09041172B1

公开(公告)日：2015-05-26

申请号：US14105473

申请日：2013-12-13

Applicant: Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

Inventor： Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/84 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Abstract translation: 本发明一般涉及一种半导体器件，更具体地，涉及优化功率半导体器件的蠕变寿命距离及其制备方法。 功率半导体器件包括具有管芯焊盘的芯片安装单元和以等间距方式靠近管芯焊盘的一个侧边缘并排设置的多个引线，附接在管芯焊盘上的半导体芯片，以及 塑料包装体覆盖模片，半导体芯片，其中塑料包装体包括覆盖引线的引线肩部的至少一部分的塑料延伸部分，以在半导体器件的端子之间获得更好的电气安全距离，因此电压 设备的爬坡距离增加。