公开(公告)号：US20070210437A1

公开(公告)日：2007-09-13

申请号：US11714906

申请日：2007-03-07

申请人： Takashi Noma ,  Shigeki Otsuka ,  Yuichi Morita ,  Kazuo Okada ,  Hiroshi Yamada ,  Katsuhiko Kitagawa ,  Noboru Okubo ,  Shinzo Ishibe ,  Hiroyuki Shinogi

发明人： Takashi Noma ,  Shigeki Otsuka ,  Yuichi Morita ,  Kazuo Okada ,  Hiroshi Yamada ,  Katsuhiko Kitagawa ,  Noboru Okubo ,  Shinzo Ishibe ,  Hiroyuki Shinogi

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00

摘要： A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.

摘要翻译： 封装的半导体器件通过简化的制造工艺制造，并且在成本，厚度和尺寸方面都降低了。 在半导体衬底上形成与器件部件连接的器件部件和焊盘电极。 支撑体通过粘合剂层结合到半导体衬底的顶表面。 然后，形成保护层，该保护层在与焊盘电极对应的位置处具有开口，并且覆盖半导体衬底的侧表面和后表面。 在与保护层中形成的开口相对应的位置处，在焊盘电极上形成导电端子。 在半导体基板的背面没有形成布线层或导电端子。 导电端子形成在半导体衬底的侧表面之外和旁边的支撑体的周边上。

公开(公告)号：US20070166955A1

公开(公告)日：2007-07-19

申请号：US11642958

申请日：2006-12-21

申请人： Takashi Noma

发明人： Takashi Noma

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L27/14618 ,  H01L23/3164 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14687 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06154 ,  H01L2224/10125 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14135 ,  H01L2224/14154 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81141 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： The invention provides a package type semiconductor device and a method of manufacturing the same where reliability and yield are enhanced without making a manufacturing process complex. A resin layer and a supporting body are formed on a front surface of a semiconductor substrate formed with a pad electrode. Then, the resin layer and the supporting body are removed by etching so as to expose the pad electrode. By this etching, the supporting body in two conductive terminal formation regions facing each other over a dicing line and the supporting body in a region connecting with these regions therebetween are simultaneously removed to form an opening, as shown in FIG. 3C. Then, a metal layer is formed on the pad electrode exposed in the opening, and a conductive terminal is further formed thereon. Lastly, dicing is performed along the dicing line to separate the semiconductor substrate in individual semiconductor dies.

摘要翻译： 本发明提供一种封装型半导体器件及其制造方法，其可靠性和产率在不使制造工艺复杂化的情况下得到增强。 树脂层和支撑体形成在形成有焊盘电极的半导体衬底的前表面上。 然后，通过蚀刻去除树脂层和支撑体，以露出焊盘电极。 通过该蚀刻，同时去除在切割线上彼此相对的两个导电端子形成区域中的支撑体和与其间的这些区域连接的区域中的支撑体，以形成开口，如图1所示。 然后，在暴露在开口中的焊盘电极上形成金属层，并且还在其上形成导电端子。 最后，沿着切割线进行切割以在单个半导体管芯中分离半导体衬底。

公开(公告)号：US07233135B2

公开(公告)日：2007-06-19

申请号：US10913354

申请日：2004-08-09

申请人： Takashi Noma ,  Hiroshi Takemura

发明人： Takashi Noma ,  Hiroshi Takemura

IPC分类号： G05F1/565 ,  G05F1/56

CPC分类号： H02M3/156

摘要： A ripple converter includes a transistor for switching an input direct-current voltage, a choke coil and a smoothing capacitor for smoothing the switched direct-current voltage, a flywheel diode for causing a current to flow through the choke coil when the transistor is turned off, and a comparing unit for controlling the ON/OFF of the transistor according to ripple in an output voltage. In the ripple converter, a waveform converter is provided on a connecting path between an output terminal and a non-inverting input terminal of a comparator in the comparing unit. A result of converting the waveform of the output voltage is compared with a reference voltage, and a result of the comparison is fed back to the transistor.

摘要翻译： 纹波转换器包括用于切换输入直流电压的晶体管，用于平滑切换的直流电压的扼流线圈和平滑电容器;当晶体管截止时，用于使电流流过扼流线圈的续流二极管 以及用于根据输出电压中的纹波来控制晶体管的导通/截止的比较单元。 在纹波转换器中，波形转换器设置在比较单元中的比较器的输出端子和非反相输入端子之间的连接路径上。 将输出电压的波形转换的结果与参考电压进行比较，将比较结果反馈给晶体管。

公开(公告)号：US20070075425A1

公开(公告)日：2007-04-05

申请号：US11529553

申请日：2006-09-29

申请人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

发明人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/562 ,  H01L23/564 ,  H01L2221/6834 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16237 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/00014

摘要： The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.

摘要翻译： 本发明防止半导体器件的外部连接的焊盘电极被损坏。 连接到电子电路的电子电路，第一焊盘电极和连接到第一焊盘电极的第二焊盘电极形成在半导体衬底上。 形成第一保护膜，覆盖第一焊盘电极并且仅在第二焊盘电极上具有开口。 进一步形成布线层，其通过穿透半导体衬底的通孔连接到第一焊盘电极的背面并从通孔延伸到半导体衬底的背面。

公开(公告)号：US07199561B2

公开(公告)日：2007-04-03

申请号：US10554523

申请日：2005-04-27

申请人： Takashi Noma

发明人： Takashi Noma

IPC分类号： G05F1/613

CPC分类号： H02M3/285 ,  H02M3/1588 ,  Y02B70/1466

摘要： In a converter device, an N-type FET is connected in series between an input terminal and an output terminal and an N-type FET is connected between the side of the output terminal of the N-type FET1 and a ground terminal. A smoothing circuit and a comparator circuit are connected to the side of the output terminal of the circuits. The output side of the comparator circuit is connected to an H/S driver circuit controlling the N-type FET1 through an inverter and directly connected to an L/S driver circuit controlling the N-type FET2. A reference voltage correction circuit is included in the comparator circuit, and the comparator circuit outputs an appropriate switching control signal by comparing a correction reference voltage, obtained through comparison of a divider voltage in accordance with the time average value of an output voltage with a reference voltage, with the divider voltage.

摘要翻译： 在转换器装置中，N型FET串联连接在输入端子和输出端子之间，N型FET连接在N型FET <1 / SUB>的输出端子侧 >和地面终端。 平滑电路和比较器电路连接到电路的输出端的一侧。 比较器电路的输出侧通过逆变器连接到控制N型FET <1>的H / S驱动电路，并直接连接到控制N型FET的L / S驱动电路， SUB> 2 。 参考电压校正电路包括在比较器电路中，并且比较器电路通过将根据输出电压的时间平均值与参考电压的分压电压进行比较而获得的校正参考电压进行比较来输出适当的开关控制信号 电压，分压电压。

公开(公告)号：US20070013353A1

公开(公告)日：2007-01-18

申请号：US10554523

申请日：2005-04-27

申请人： Takashi Noma

发明人： Takashi Noma

IPC分类号： G05F1/00

CPC分类号： H02M3/285 ,  H02M3/1588 ,  Y02B70/1466

摘要： In a converter device, an N-type FET is connected in series between an input terminal and an output terminal and an N-type FET is connected between the side of the output terminal of the N-type FET, and a ground terminal. A smoothing circuit and a comparator circuit are connected to the side of the output terminal of the circuits. The output side of the comparator circuit is connected to an H/S driver circuit controlling the N-type FET1 through an inverter and directly connected to an L/S driver circuit controlling the N-type FET2. A reference voltage correction circuit is included in the comparator circuit, and the comparator circuit outputs an appropriate switching control signal by comparing a correction reference voltage, obtained through comparison of a divider voltage in accordance with the time average value of an output voltage with a reference voltage, with the divider voltage.

摘要翻译： 在转换器装置中，N型FET串联连接在输入端子和输出端子之间，N型FET连接在N型FET的输出端子侧和接地端子之间。 平滑电路和比较器电路连接到电路的输出端的一侧。 比较器电路的输出侧通过逆变器连接到控制N型FET <1>的H / S驱动电路，并直接连接到控制N型FET的L / S驱动电路， SUB> 2 。 参考电压校正电路包括在比较器电路中，并且比较器电路通过将根据输出电压的时间平均值与参考电压的分压电压进行比较而获得的校正参考电压进行比较来输出适当的开关控制信号 电压，分压电压。

公开(公告)号：US20070001302A1

公开(公告)日：2007-01-04

申请号：US11451633

申请日：2006-06-13

申请人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

发明人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3192 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

摘要翻译： 本发明提供了一种具有高可靠性的CSP型半导体器件。 半导体器件包括形成在半导体衬底上的焊盘电极，覆盖焊盘电极的端部并且在焊盘电极上具有第一开口的第一钝化膜，形成在第一开口中的焊盘电极上的镀层，第二钝化膜 钝化膜，覆盖第一钝化膜的端部与镀覆层之间的焊盘电极的露出部分，覆盖镀层的端部，并且在镀层上具有第二开口;以及导电端子， 第二开口中的镀层。

公开(公告)号：US07112881B2

公开(公告)日：2006-09-26

申请号：US10945945

申请日：2004-09-22

申请人： Takayuki Kaida ,  Ryu Shimizu ,  Mitsuru Okigawa ,  Tetsuya Miwa ,  Takashi Noma

发明人： Takayuki Kaida ,  Ryu Shimizu ,  Mitsuru Okigawa ,  Tetsuya Miwa ,  Takashi Noma

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/43

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/15788 ,  H01L2924/00

摘要： A semiconductor device allowing simplification of a fabrication process is provided. This semiconductor device comprises a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit, a first wire formed to be in contact with the upper surface of the first insulator film and a second wire formed to extend along the side surface and the lower surface of the semiconductor chip and connected to the lower surface of the first wire exposed by partially removing the first insulator film.

摘要翻译： 提供了允许简化制造工艺的半导体器件。 该半导体器件包括由单一材料构成的第一绝缘膜，其形成为与包括电路的半导体芯片的上表面接触，形成为与第一绝缘膜的上表面接触的第一线和 形成为沿着半导体芯片的侧表面和下表面延伸并连接到通过部分去除第一绝缘膜而暴露的第一线的下表面的第二线。

公开(公告)号：US20060068572A1

公开(公告)日：2006-03-30

申请号：US11225898

申请日：2005-09-14

申请人： Takashi Noma ,  Kazuo Okada ,  Hiroshi Yamada ,  Masanori Iida

发明人： Takashi Noma ,  Kazuo Okada ,  Hiroshi Yamada ,  Masanori Iida

IPC分类号： H01L21/28 ,  H01L29/70 ,  H01L21/44 ,  H01L27/102 ,  H01L27/082 ,  H01L31/11

CPC分类号： H01L24/12 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/00014

摘要： The invention is directed to improvement of reliability of a chip size package type semiconductor device in a manufacturing method thereof. A support body is formed on a front surface of a semiconductor substrate with a first insulation film therebetween. Then, a part of the semiconductor substrate is selectively etched from its back surface to form an opening, and then a second insulation film is formed on the back surface. Next, the first insulation film and the second insulation film at a bottom of the opening are selectively etched, to expose pad electrodes at the bottom of the opening. Then, a third resist layer is selectively formed on a second insulation film at boundaries between sidewalls and the bottom of the opening on the back surface of the semiconductor substrate. Furthermore, a wiring layer electrically connected with the pad electrodes at the bottom of the opening and extending onto the back surface of the semiconductor substrate is selectively formed corresponding to a predetermined pattern.

摘要翻译： 本发明的目的在于提高芯片尺寸封装型半导体器件的制造方法的可靠性。 在半导体基板的前表面上形成有第一绝缘膜的支撑体。 然后，从其背面选择性地蚀刻半导体衬底的一部分以形成开口，然后在背面形成第二绝缘膜。 接下来，选择性地蚀刻开口底部的第一绝缘膜和第二绝缘膜，以露出开口底部的焊盘电极。 然后，在半导体衬底的背面的开口的侧壁和底部之间的边界处，在第二绝缘膜上选择性地形成第三抗蚀剂层。 此外，根据预定图案选择性地形成与开口底部的焊盘电极电连接并延伸到半导体衬底的背面上的布线层。

公开(公告)号：US20060033198A1

公开(公告)日：2006-02-16

申请号：US11206146

申请日：2005-08-18

申请人： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

发明人： Takashi Noma ,  Hiroyuki Shinogi ,  Nobuyuki Takai ,  Katsuhiko Kitagawa ,  Ryoji Tokushige ,  Takayasu Otagaki ,  Tatsuya Ando ,  Mitsuru Okigawa

IPC分类号： H01L23/04

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

摘要翻译： 具有球形导电端子的BGA（球栅阵列）型半导体器件降低了成本并提高了可靠性。 第一布线形成在形成在半导体管芯的表面上的绝缘膜上。 在半导体管芯的表面上接合玻璃基板，半导体管芯的侧表面和背面被绝缘膜覆盖。 第二布线连接到第一布线的侧表面或后表面并在半导体管芯的后表面上延伸。 导电端子如凸块形成在第二布线上。