公开(公告)号：US09997463B2

公开(公告)日：2018-06-12

申请号：US15191359

申请日：2016-06-23

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L23/538 ,  H01L29/417 ,  H01L29/775 ,  H01L29/792 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

公开(公告)号：US20180061817A1

公开(公告)日：2018-03-01

申请号：US15802525

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09905706B2

公开(公告)日：2018-02-27

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/30 ,  H01L29/84 ,  H01H59/00 ,  B82B3/00 ,  H01H1/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US20180047849A1

公开(公告)日：2018-02-15

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US09825055B2

公开(公告)日：2017-11-21

申请号：US14802996

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/04 ,  H01L27/12 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/161 ,  H01L29/78 ,  H01L23/528 ,  H01L27/112 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

公开(公告)号：US20170219771A1

公开(公告)日：2017-08-03

申请号：US15491718

申请日：2017-04-19

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: G02B6/132 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US09646939B2

公开(公告)日：2017-05-09

申请号：US15090996

申请日：2016-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

公开(公告)号：US09633986B2

公开(公告)日：2017-04-25

申请号：US15175738

申请日：2016-06-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L49/02 ,  H01L27/01 ,  H01L23/525 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

公开(公告)号：US09601630B2

公开(公告)日：2017-03-21

申请号：US13931096

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

公开(公告)号：US20170005106A1

公开(公告)日：2017-01-05

申请号：US15191359

申请日：2016-06-23

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L23/538 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L27/07

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

Abstract translation: 模块化互连结构有助于从垂直GAA FET构建复杂而紧凑的集成电路。 模块化互连结构包括到晶体管端子的环形金属触点，从垂直纳米线径向向外延伸的堆叠盘的扇区，以及棒形式的通孔。 安装在径向扇形互连上的延伸片允许信号从每个晶体管端子扇出。 相邻互连由线性段链接。 与常规集成电路不同，如本文所述的模块化互连在晶体管的同时形成。 垂直GAA NAND和NOR门提供构建块，用于创建所有类型的逻辑门，以执行任何所需的布尔逻辑功能。 堆叠的垂直GAA FET通过模块化互连结构成为可能。 模块化互连结构允许使用标准CMOS工艺将各种专用垂直GAA器件集成在硅衬底上。