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    Method of stressing a semiconductor layer
    132.
    发明授权
    Method of stressing a semiconductor layer 有权
    强化半导体层的方法

    公开(公告)号：US09318372B2

    公开(公告)日：2016-04-19

    申请号：US14526053

    申请日：2014-10-28

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

    Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

    IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02

    CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

    Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

    COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE
    136.
    发明申请
    COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE 有权
    包装系统的通讯安排

    公开(公告)号：US20130142227A1

    公开(公告)日：2013-06-06

    申请号：US13651883

    申请日：2012-10-15

    Applicant: STMicroelectronics SA ,  STMicroelectronics (R&D) Ltd ,  STMicroelectronics (Grenoble 2) SAS

    Inventor： Andrew FERRIS ,  Ignazio Antonino URZI ,  Pascal TEISSIER

    IPC: H04B1/38

    CPC classification number: G06F13/423

    Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

    Abstract translation: 电路包括第一n比特通信块和第二m比特通信块。 控制器被配置为控制第一和第二通信块的操作模式。 在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。 在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。

    METHOD AND DEVICE FOR PROCESSING THE DC OFFSET OF A RADIOFREQUENCY RECEPTION SUBSYSTEM
    138.
    发明申请
    METHOD AND DEVICE FOR PROCESSING THE DC OFFSET OF A RADIOFREQUENCY RECEPTION SUBSYSTEM 审中-公开
    用于处理无线电接收子系统的直流偏移的方法和装置

    公开(公告)号：US20100020903A1

    公开(公告)日：2010-01-28

    申请号：US12505629

    申请日：2009-07-20

    Applicant: Antoine HUE ,  Gabriel DELLA-MONICA ,  Florent SIBILLE

    Inventor： Antoine HUE ,  Gabriel DELLA-MONICA ,  Florent SIBILLE

    IPC: H04L25/06

    CPC classification number: H04L25/063

    Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.

    Abstract translation: 一种方法可以补偿射频接收装置中的直流（DC）偏移。 该方法可以包括将接收设备的模拟部分划分成多个区域，对于每个区域，校准要在相应区域的操作范围内施加的初始DC偏移补偿，其它区域的操作范围被限制为 阈值操作范围，以及基于所述基本DC偏移补偿，确定在所述操作范围内对所述接收装置施加的DC偏移补偿。

    Electronic circuit comprising a RF switches having reduced parasitic capacitances
    140.
    发明授权
    Electronic circuit comprising a RF switches having reduced parasitic capacitances 有权

    公开(公告)号：US12293981B2

    公开(公告)日：2025-05-06

    申请号：US17733589

    申请日：2022-04-29

    Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

    Inventor： Stephane Monfray ,  Siddhartha Dhar ,  Alain Fleury

    IPC: H01L23/66 ,  H01L21/48 ,  H01L23/373 ,  H01L23/42 ,  G11C13/00 ,  H10N70/00

    Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

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