公开(公告)号：US20170018302A1

公开(公告)日：2017-01-19

申请号：US14822911

申请日：2015-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Yu-Cheng Tung ,  Chin-Sheng Yang

IPC: G11C11/412 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Abstract translation: 静态随机存取存储器单元结构和布局结构包括两个上拉晶体管，两个下拉晶体管，两个槽接触插头和两个金属零互连。 每个金属零互连设置在每个槽接触插头和每个上拉晶体管的栅极上，每个槽接触插塞跨越每个下拉晶体管的漏极和每个上拉晶体管的漏极延伸到 跨越每个金属零互连的一端。 槽接触插塞之间的间隙小于金属零互连之间的间隙。

公开(公告)号：US09543211B1

公开(公告)日：2017-01-10

申请号：US14864881

申请日：2015-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Wei-Hao Huang ,  Chih-Sen Huang ,  Ching-Wen Hung

IPC: H01L21/70 ,  H01L21/8234 ,  H01L21/283 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.

Abstract translation: 半导体结构的制造方法包括以下步骤。 栅极结构形成在半导体衬底上。 在两个相邻栅极结构之间形成源极/漏极接触。 源极/漏极接触器通过凹陷工艺凹陷。 源极/漏极接触件的顶表面在凹陷过程之后低于栅极结构的顶表面。 在凹陷过程之后，在栅极结构和源极/漏极触点上形成阻挡层。 源极/漏极接触点上的阻挡层的顶表面低于栅极结构的顶表面。 半导体结构包括半导体衬底，栅极结构，栅极接触结构和源极/漏极接触。 源极/漏极触点设置在两个相邻的栅极结构之间，源极/漏极接触的顶表面低于栅极结构的顶部表面。

公开(公告)号：US20170005181A1

公开(公告)日：2017-01-05

申请号：US14820565

申请日：2015-08-07

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/283 ,  H01L21/308 ,  H01L21/31 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/845

Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

Abstract translation: 半导体器件包括分开设置在半导体衬底上的第一鳍状结构和第二鳍状结构。 第一和第二鳍状结构中的每一个包括基部和从顶部突出的顶部。 第二鳍状结构的基部比第二鳍状结构的顶部宽，并且第二鳍状结构的顶部与第一鳍状结构的顶部一样宽。 每个第二鳍状结构还包括在其侧壁上的凹陷区域。

公开(公告)号：US20170005008A1

公开(公告)日：2017-01-05

申请号：US14814516

申请日：2015-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.

Abstract translation: 一种用于制造具有栅极结构的半导体器件的方法，包括形成包括至少两个鳍状结构的衬底，所述鳍结构从衬底的顶表面突出，所述衬底包括第一凹部和设置在第一凹部下方的第二凹部， 并且所述第二凹部设置在所述翅片结构之间，其中所述第一凹部的宽度大于所述第二凹部的宽度，并且所述第一凹部和所述第二凹部形成台阶结构; 在所述第二凹部中形成绝缘结构; 以及在所述绝缘结构上形成所述栅极结构，其中所述第一凹槽和所述第二凹槽被所述栅极结构和所述绝缘结构填充。

公开(公告)号：US20160372381A1

公开(公告)日：2016-12-22

申请号：US15255316

申请日：2016-09-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin.

Abstract translation: 一种制造半导体器件的方法包括：首先，提供包括从衬底表面突出的第一子鳍和第二副鳍的半导体鳍。 然后在半导体翅片中设置具有延伸在其中的开口的隔离结构，以电隔离第一子鳍和第二子鳍。 随后，形成第一虚拟结构，该第一虚拟结构设置在第一隔离结构上并具有沿着半导体鳍片的长轴与第一隔离结构完全重叠的至少一个金属层，其中金属层侧向共形地向下延伸到开口中并延伸 沿着半导体鳍片的长轴向上超过第一隔离结构，以形成在开口的侧壁和底部上重叠的阶梯结构，第一子鳍片的一部分和第二子鳍片的一部分。

公开(公告)号：US20160240629A1

公开(公告)日：2016-08-18

申请号：US14621358

申请日：2015-02-12

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

Abstract translation: 用于形成具有不同间距的门的半导体工艺包括以下步骤。 栅极层形成在基板上。 第一心轴和第二心轴分别形成在栅极层上。 形成第一间隔材料以保形地覆盖第一心轴但暴露第二心轴。 形成第二间隔材料以共形地覆盖第一间隔物材料和第二心轴。 蚀刻第一间隔物材料和第二间隔物材料以在第一心轴旁边形成第一间隔物，同时在第二心轴旁边形成第二间隔物。 去除第一心轴和第二心轴。 第一间隔物和第二间隔物的布置被转移到栅极层，从而形成第一栅极和第二栅极。 此外，还提供了分别形成第一间隔件和第二间隔件的半导体工艺。

公开(公告)号：US20160233301A1

公开(公告)日：2016-08-11

申请号：US14663464

申请日：2015-03-20

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a substrate, a first nanowire structure disposed on the substrate, and the first nanowire structure includes a gate region and a source/drain region The diameter of the first nanowire structure within the gate region is different from the diameter of the first nanowire structure within the source/drain region.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板上的第一纳米线结构，第一纳米线结构包括栅极区域和源极/漏极区域。栅极区域内的第一纳米线结构的直径不同于 源极/漏极区域内的第一纳米线结构的直径。

公开(公告)号：US09349607B1

公开(公告)日：2016-05-24

申请号：US14792630

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0273 ,  H01L21/3086

Abstract: A method of forming a line pattern including following steps. First of all, a substrate having a first region and a second region is provided. Next, a directed self-assembly (DSA) material layer is formed on the substrate, covering the first region and the second region. Then, the DSA material layer in the second region is removed, to form a patterned DSA material layer. After these, an annealing process is performed to enable only the DSA material layer in the first region and to form a plurality of first stripe structures and a plurality of second stripe structures arranged alternately in a first direction.

Abstract translation: 一种形成包括以下步骤的线条图案的方法。 首先，提供具有第一区域和第二区域的基板。 接下来，在衬底上形成定向自组装（DSA）材料层，覆盖第一区域和第二区域。 然后，去除第二区域中的DSA材料层，以形成图案化的DSA材料层。 之后，进行退火处理，以仅使第一区域中的DSA材料层能够形成多个第一条纹结构和沿第一方向交替布置的多个第二条纹结构。

公开(公告)号：US09324620B2

公开(公告)日：2016-04-26

申请号：US14462574

申请日：2014-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-Xiong Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract translation: 金属栅极结构包括具有致密区域和iso区域的基板。 第一金属栅极结构设置在致密区域内，第二金属栅极结构设置在iso区域内。 第一金属栅极结构包括设置在密集区域内的第一沟槽和设置在第一沟槽内的第一金属层。 第二金属栅极结构包括设置在iso区内的第二沟槽和设置在第二沟槽内的第二金属层。 第二金属层的高度大于第一金属层的高度。

公开(公告)号：US20160099181A1

公开(公告)日：2016-04-07

申请号：US14539175

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate. The first isolation structure is disposed in the semiconductor fin used for electrically isolating the first sub-fin and the second sub-fin. The first dummy structure is disposed on the first isolation structure and laterally extends beyond the first isolation structure along a long axis of the semiconductor fin, so as to partially overlap a portion of the first sub-fin and a portion of the second sub-fin.

Abstract translation: 半导体器件包括衬底，半导体鳍片，第一隔离结构和第一虚拟结构。 半导体鳍片包括从衬底的表面突出的第一子鳍片和第二子鳍片。 第一隔离结构设置在用于电隔离第一子鳍片和第二子鳍片的半导体鳍片中。 第一虚拟结构设置在第一隔离结构上，并且沿着半导体翅片的长轴横向延伸超过第一隔离结构，从而部分地与第一子鳍的一部分和第二子鳍的一部分重叠 。