公开(公告)号：US08466514B2

公开(公告)日：2013-06-18

申请号：US13274642

申请日：2011-10-17

申请人： Fu-Yuan Hsieh

发明人： Fu-Yuan Hsieh

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2924/13055 ,  H01L2924/00

摘要： A trench semiconductor power device integrated with four types of ESD clamp diodes for optimization of total perimeter of the ESD clamp diodes, wherein the ESD clamp diodes comprise multiple back to back Zener diodes with alternating doped regions of a first conductivity type next to a second conductivity type, wherein each of the doped regions has a closed ring structure.

摘要翻译： 一种与四种类型的ESD钳位二极管集成的沟槽半导体功率器件，用于优化ESD钳位二极管的总周边，其中ESD钳位二极管包括多个背靠背齐纳二极管，其具有紧邻第二导电性的第一导电类型的交替掺杂区域 型，其中每个掺杂区具有闭环结构。

公开(公告)号：US20130020633A1

公开(公告)日：2013-01-24

申请号：US13627709

申请日：2012-09-26

申请人： FUJI Electric Co., Ltd.

发明人： Noriyuki IWAMURO

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

公开(公告)号：US20120326207A1

公开(公告)日：2012-12-27

申请号：US13491581

申请日：2012-06-07

申请人： Kenichi Yoshimochi

发明人： Kenichi Yoshimochi

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L21/76237 ,  H01L21/76205 ,  H01L21/763 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/11896 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66106 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/866 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/039 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4911 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L21/78 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

摘要翻译： 半导体器件包括：第一导电型半导体层，包括其中形成有杂质区的晶体管的有源区和围绕有源区的边缘区;形成在有源区和边界之间的第二导电型沟道层; 形成半导体层的前表面，形成在有源区中的至少一个栅极沟槽，以从半导体层的前表面延伸通过沟道层，形成在栅极沟槽的内表面上的栅极绝缘膜， 形成在栅极沟槽中的栅极绝缘膜内部的栅极电极，以及布置在有源区域和边缘区域之间的至少一个隔离沟槽，以围绕有源区域并且从半导体层的前表面延伸穿过沟道层， 隔离沟槽的深度等于栅极沟槽的深度。

公开(公告)号：US08299522B2

公开(公告)日：2012-10-30

申请号：US13049463

申请日：2011-03-16

申请人： Noriyuki Iwamuro

发明人： Noriyuki Iwamuro

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

摘要： A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

摘要翻译： 以这样的方式配置超结半导体衬底，使得并联pn结构的n型半导体层与有源区和外围抗击结构区之间的边界区域相对。 在位于上述n型半导体层的两侧的p型半导体层之间的中心处形成高浓度区域。 在n型半导体层上形成有源极与沟道层接触的区域。 高浓度区域与沟道层接触的部分用作二极管。 二极管的击穿电压设置为低于器件的击穿电压。

公开(公告)号：US20120241856A1

公开(公告)日：2012-09-27

申请号：US13486738

申请日：2012-06-01

申请人： Yoshito NAKAZAWA ,  Yuji YATSUDA

发明人： Yoshito NAKAZAWA ,  Yuji YATSUDA

IPC分类号： H01L29/78

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。

公开(公告)号：US20120241848A1

公开(公告)日：2012-09-27

申请号：US13234045

申请日：2011-09-15

申请人： Takeshi UCHIHARA

发明人： Takeshi UCHIHARA

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7809

摘要： A semiconductor element includes a drain layer, a drift region selectively provided in the drain layer, a base region selectively provided in the drift region, a source region selectively provided in the base region, first and/or second metal layers selectively provided in at least one of the source region and the drain layer from the front surface to the inside of at least one of the source region and the drain layer, a gate electrode in a trench shape extending in a direction substantially parallel to the front surface of the drain layer from a part of the source region through the base region adjacent to at least the part of the source region to a part of the drift region, a source electrode connected to the first metal layer, and a drain electrode connected to the drain layer or the second metal layer.

摘要翻译： 半导体元件包括漏极层，选择性地设置在漏极层中的漂移区域，选择性地设置在漂移区域中的基极区域，选择性地设置在基极区域中的源极区域，至少选择性地设置有第一和/或第二金属层 源极区域和漏极层中的至少一个源极区域和漏极层中的一个源极区域和漏极层中的至少一个的沟槽形状的栅极电极，其沿与漏极层的前表面基本平行的方向延伸 从源极区域的一部分穿过与源极区域的至少一部分相邻的基极区域到漂移区域的一部分，连接到第一金属层的源极电极和连接到漏极层或漏极区域的漏极电极 第二金属层。

公开(公告)号：US20120187478A1

公开(公告)日：2012-07-26

申请号：US13499599

申请日：2009-10-01

申请人： Hidefumi Takaya

发明人： Hidefumi Takaya

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7808

摘要： Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring.

摘要翻译： 即使在半导体装置中发生雪崩现象的情况下，也能够抑制特性劣化的半导体装置。 半导体器件包括第一导电型漂移区; 设置在所述漂移区域的前表面侧的第二导电型体区域; 穿过身体区域并延伸到漂移区域的栅极沟槽; 设置在所述栅极沟槽内的栅电极; 设置在所述栅极电极和所述栅极沟槽的壁表面之间的绝缘体; 以及围绕所述栅极沟槽的底部的第二导电型扩散区域。 调整扩散区域的杂质浓度和尺寸，使得当发生雪崩现象时，在扩散区域和漂移区域之间的p-n结处发生击穿。

公开(公告)号：US08217419B2

公开(公告)日：2012-07-10

申请号：US12664841

申请日：2008-06-13

申请人： Masaru Takaishi

发明人： Masaru Takaishi

IPC分类号： H01L29/66

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7839 ,  H01L29/866 ,  H01L29/872

摘要： Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

摘要翻译： 提供了其中导通电阻大大降低的半导体器件。 在半导体器件20的N型外延层（2）的区域（2a）中，相邻沟槽（3）之间的每个区域被形成在沟槽（3）周围的耗尽层（14）阻挡，使得电流通道 （12）中断，而形成在沟槽（3）周围的耗尽层（14）的一部分被删除，使得电流通道（12）打开。 在区域（2b）中，N型外延层（2）与P +型扩散区（7）之间的接合部（8）形成齐纳二极管（8）。

公开(公告)号：US20120142156A1

公开(公告)日：2012-06-07

申请号：US13396816

申请日：2012-02-15

申请人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

发明人： Hiroshi Inagawa ,  Nobuo Machida ,  Kentaro Oishi

IPC分类号： H01L21/8234

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

摘要翻译： 在绝缘栅型半导体器件中，其中栅极用导电层嵌入到形成在半导体衬底中的沟槽中，并且源极导电层设置在半导体衬底的主表面上，一部分 由栅极用导电层和用于封盖栅极导电层的上表面的帽绝缘膜构成的栅极柱从半导体基板的主表面突出; 侧壁间隔件设置在门柱的突出部分的侧壁上; 并且源极导电层连接到由侧壁间隔物限定的半导体衬底的主表面的接触区域。

公开(公告)号：US20120133388A1

公开(公告)日：2012-05-31

申请号：US13389194

申请日：2009-08-18

申请人： Beatrice Bernoux ,  Rene Escoffier ,  Jean Reynes

发明人： Beatrice Bernoux ,  Rene Escoffier ,  Jean Reynes

IPC分类号： G01R31/26 ,  H01L27/105

CPC分类号： H01L29/7808 ,  G01R31/129 ,  G01R31/275 ,  H01L24/05 ,  H01L29/0696 ,  H01L29/7815 ,  H01L2224/04042 ,  H01L2224/4847 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device. A measured current is applied between a first location on an elongate strip element of the monitor conductive layer and a first location on one of a pair of lateral extensions of the strip, and the corresponding voltage developed between a second location on the elongate strip element and the other of said pair of lateral extensions is measured.

摘要翻译： 一种晶体管功率开关器件，包括用于承载半导体本体的第一和第二面之间的电流的垂直晶体管元件阵列。 该器件还包括半导体监测元件，其包括半导体主体中的第一和第二半导体监测区域以及与晶体管阵列的载流导电层不同的监测导电层。 半导体监测元件呈现代表晶体管阵列的半导体特性。 测量半导体监测元件的特性代表晶体管阵列的特性。 晶体管功率开关器件的源极金属老化通过测量和记录当晶体管功率开关器件新的时候是监测导电层的薄层电阻的函数并将其与器件操作后的值进行比较来监测参数。 测量的电流施加在监视器导电层的细长带状元件上的第一位置和条带的一对横向延伸部之一上的第一位置之间，以及在细长带状元件上的第二位置之间产生的对应电压和 测量所述一对侧向延伸部中的另一个。