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公开(公告)号：US09831288B2
公开(公告)日：2017-11-28
申请号：US15387850
申请日：2016-12-22
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor： Laurent Grenouillet , Sotirios Athanasiou , Philippe Galy
CPC classification number: H01L27/2454 , G11C13/0007 , G11C13/0069 , G11C2213/53 , H01L27/101 , H01L27/1207 , H01L27/2436 , H01L28/00 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/147
Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
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公开(公告)号：US20170336560A1
公开(公告)日：2017-11-23
申请号：US15377848
申请日：2016-12-13
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frederic Boeuf , Charles Baudot
CPC classification number: G02B6/12002 , G02B6/12004 , G02B6/122 , G02B6/124 , G02B6/126 , G02B6/2773 , G02B6/30 , G02B6/34 , G02B6/4204 , G02B2006/12104 , G02B2006/12107 , G02B2006/12116 , G02B2006/12147
Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
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公开(公告)号：US20170317275A1
公开(公告)日：2017-11-02
申请号：US15654405
申请日：2017-07-19
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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144.发明申请公开(公告)号：US20170317106A1
公开(公告)日：2017-11-02
申请号：US15361937
申请日：2016-11-28
Inventor： Philippe Boivin , Franck Arnaud , Gregory Bidal , Dominique Golanski , Emmanuel Richard
CPC classification number: H01L27/1207 , H01L29/0653 , H01L29/0847 , H01L29/4916
Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.
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公开(公告)号：US20170299651A1
公开(公告)日：2017-10-19
申请号：US15378663
申请日：2016-12-14
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sylvain Clerc
IPC: G01R31/28
CPC classification number: G01R31/2882 , G01R31/3016 , G01R31/31725 , H03K5/133 , H03K19/00369
Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.
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Patent Agency Ranking
公开(公告)号：US09793321B2
公开(公告)日：2017-10-17
申请号：US14970347
申请日：2015-12-15
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US09791346B1
公开(公告)日：2017-10-17
申请号：US15133614
申请日：2016-04-20
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Jean-Francois Carpentier , Patrick Lemaitre , Jean-Robert Manouvrier , Charles Baudot , Bertrand Borot
CPC classification number: G01M11/02 , G01R31/2656 , G01R31/27 , G01R31/2884 , G01R31/303 , G01R31/311 , G01R31/31728 , G01R35/00 , G02B6/00 , G02B6/12004 , G02B6/2808 , G02B6/34
Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.
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148.发明授权公开(公告)号：US09759546B2
公开(公告)日：2017-09-12
申请号：US14442081
申请日：2013-09-19
Applicant: SOITEC , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Oleg Kononchuk , Didier Dutartre
CPC classification number: G01B11/06 , G01B11/0633 , G01B11/30 , G02B21/361 , H01L22/12
Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.
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149.发明授权公开(公告)号：US09735707B2
公开(公告)日：2017-08-15
申请号：US14356717
申请日：2012-11-08
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Stéphane Monfray , Guillaume Savelli , Thomas Skotnicki , Philippe Coronel , Frédéric Gaillard
Abstract: System for converting thermal energy into electrical energy (S1) intended to be arranged between a hot source (SC) and a cold source (SF), comprising means for converting thermal energy into mechanical energy (6) and a piezoelectric material, with the means for converting thermal energy into mechanical energy (6) comprising groups (G1, G2) of at least three bimetallic strips (9, 11, 13) linked mechanically together by their longitudinal ends and suspended above a substrate (12), each bimetallic strip (9, 11, 13) comprising two stable states wherein it has in each of the states a curvature, with two directly adjacent bimetallic strips (9, 11, 13) having for a given temperature opposite curvatures, with the switching from one stable state of the bimetallic strips (9, 11, 13) to the other causing the deformation of a piezoelectric material.
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150.发明申请公开(公告)号：US20170221948A1
公开(公告)日：2017-08-03
申请号：US15489265
申请日：2017-04-17
Inventor： Axel Crocherie , Michel Marty , Jean-Luc Huguenin , Sébastien Jouan
IPC: H01L27/146 , H01L29/66
CPC classification number: H01L29/66977 , H01L27/1462 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14685 , H01L2027/11892 , H04N2209/045
Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer disposed above the photodiode, a dielectric region disposed above the antireflection layer, an optical filter disposed above the dielectric region, and a diffraction grating disposed in the antireflection layer. The diffraction grating includes an array of pads.
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