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    Field effect transistor device spacers
    141.
    发明授权
    Field effect transistor device spacers 有权
    场效应晶体管器件间隔物

    公开(公告)号：US09472670B1

    公开(公告)日：2016-10-18

    申请号：US15085376

    申请日：2016-03-30

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Rama Kambhampati ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

    IPC: H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/7848

    Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

    Abstract translation: 一种用于形成场效应晶体管的方法包括在第一鳍上形成第一虚拟栅极堆叠，在第二鳍片上形成第二虚拟栅极叠层，在第一伪栅极叠层上沉积第一层间隔物材料， 虚拟栅极堆叠和第二鳍片，在第一伪栅极堆叠和第一鳍片上构图第一掩模层，蚀刻以去除第一层间隔物材料的部分并形成邻近第二伪栅极叠层的间隔区， 第一掩模层，在所述第二鳍上外延生长硅材料，在所述第一隔离层材料层上沉积氧化物层，所述第一外延材料和所述第二伪栅极堆叠，以及在所述层上沉积第二隔离层材料层 的氧化物质。

    INTEGRATED CIRCUIT PRODUCT COMPRISING LATERAL AND VERTICAL FINFET DEVICES
    143.
    发明申请
    INTEGRATED CIRCUIT PRODUCT COMPRISING LATERAL AND VERTICAL FINFET DEVICES 有权
    集成电路产品包含横向和垂直FinFET器件

    公开(公告)号：US20160293757A1

    公开(公告)日：2016-10-06

    申请号：US14931409

    申请日：2015-11-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Andreas Knorr

    IPC: H01L29/78 ,  H01L27/088

    CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

    Abstract: One example of a novel integrated circuit product disclosed herein includes, among other things, a lateral FinFET device comprising a first gate structure having a first upper surface positioned above a semiconductor substrate and a vertical FinFET device comprising a second gate structure having a second upper surface positioned above the semiconductor substrate, wherein the first upper surface of the first gate structure is positioned at a first height level above a reference surface of the semiconductor substrate and the second upper surface of the second gate structure is positioned at a second height level above the reference surface of the semiconductor substrate, the first height level being greater than the second height level.

    Abstract translation: 本文公开的新颖的集成电路产品的一个示例尤其包括横向FinFET器件，其包括具有位于半导体衬底上方的第一上表面的第一栅极结构和包括具有第二上表面的第二栅极结构的垂直FinFET器件 位于所述半导体衬底上方，其中所述第一栅极结构的所述第一上表面位于所述半导体衬底的参考表面上方的第一高度水平处，并且所述第二栅极结构的所述第二上表面位于所述第二栅极结构的第二高度水平 半导体衬底的参考表面，第一高度水平大于第二高度水平。

    Methods of forming fins for FinFET semiconductor devices and the resulting devices
    147.
    发明授权
    Methods of forming fins for FinFET semiconductor devices and the resulting devices 有权
    形成FinFET半导体器件的翅片的方法和所得到的器件

    公开(公告)号：US09449881B1

    公开(公告)日：2016-09-20

    申请号：US14710053

    申请日：2015-05-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/308 ,  H01L21/764 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681

    Abstract: A method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a mask layer above the dielectric material. The mask layer has an opening defined therein. At least one etching process is performed to remove a portion of the at least one dielectric material exposed by the opening so as to expose a top surface portion and sidewall surface portions of at least one fin in the plurality of fins. The at least one dielectric material remains above the substrate adjacent the at least one fin. An etching process is performed to remove the at least one fin.

    Abstract translation: 一种方法包括在衬底上形成多个翅片，在多个翅片之上和之间形成至少一种电介质材料，并在电介质材料之上形成掩模层。 掩模层具有限定在其中的开口。 执行至少一个蚀刻工艺以去除由开口暴露的至少一个介电材料的一部分，以暴露多个翅片中的至少一个翅片的顶表面部分和侧壁表面部分。 所述至少一个介电材料保留在与所述至少一个翅片相邻的衬底上。 进行蚀刻处理以去除至少一个翅片。

    Interconnect structures and methods of fabrication
    148.
    发明授权
    Interconnect structures and methods of fabrication 有权
    互连结构和制造方法

    公开(公告)号：US09412695B1

    公开(公告)日：2016-08-09

    申请号：US14641699

    申请日：2015-03-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hiroaki Niimi ,  Andreas Knorr

    IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532

    CPC classification number: H01L29/7851 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/66795

    Abstract: Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.

    Abstract translation: 提供了用于电路结构晶体管的方法和互连结构。 所述方法包括例如：在衬底上提供一个或多个鳍片，以及在鳍片和衬底上方的绝缘材料; 提供延伸到所述绝缘材料中的阻挡结构，所述阻挡结构沿着所述鳍片的相对侧布置; 暴露所述鳍片和所述屏障结构的一部分; 以及形成在所述翅片上延伸的互连结构，所述阻挡结构将所述互连结构限制在横向于所述鳍片的限定尺寸。 暴露鳍状物和阻挡结构的部分可以包括用蚀刻剂均匀地蚀刻绝缘材料，该蚀刻剂选择性地蚀刻绝缘材料而不影响阻挡结构的阻挡材料。

    Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
    149.
    发明授权
    Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products 有权
    在由FinFET器件和所得产品组成的集成电路产品上形成单次和双重扩散断裂的方法

    公开(公告)号：US09412616B1

    公开(公告)日：2016-08-09

    申请号：US14942448

    申请日：2015-11-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

    IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

    Abstract translation: 本文公开的一种说明性方法包括形成由第一和第二层材料构成的多层图案化掩模层，以及延伸穿过第一和第二材料层的第一和第二开口，其中第一开口是 位于基板的将形成DDB隔离结构的第一区域之上，并且第二开口位于衬底的将形成SDB隔离结构的第二区域之上。 该方法还包括通过第一开口执行第一处理操作以形成DDB隔离结构，执行第二处理操作以去除第二层材料并露出第一层材料中的第一开口，以及执行第三工艺 通过第二次开启操作形成SDB隔离结构。

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