公开(公告)号：US20170170296A1

公开(公告)日：2017-06-15

申请号：US14964546

申请日：2015-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chueh-Yang Liu ,  Yu-Ying Lin ,  I-cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/02587 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.

公开(公告)号：US09646889B1

公开(公告)日：2017-05-09

申请号：US15003782

申请日：2016-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/7845 ,  H01L21/02065 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.

公开(公告)号：US09633904B1

公开(公告)日：2017-04-25

申请号：US15352528

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Neng-Hui Yang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306 ,  H01L29/167 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.

公开(公告)号：US09627534B1

公开(公告)日：2017-04-18

申请号：US14946795

申请日：2015-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/26 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L23/00 ,  H01L23/535 ,  H01L29/267 ,  H01L21/265

CPC classification number: H01L21/0335 ,  H01L21/02521 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.

公开(公告)号：US09613808B1

公开(公告)日：2017-04-04

申请号：US15001094

申请日：2016-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/32139

Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.

公开(公告)号：US20160276431A1

公开(公告)日：2016-09-22

申请号：US14658262

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/161 ,  H01L21/306

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US09449829B1

公开(公告)日：2016-09-20

申请号：US14705960

申请日：2015-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Tung Hsiao ,  Chien-Liang Lin ,  Yu-Ren Wang

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate. A barrier layer is formed on the dielectric layer. An ammonia thermal treatment process with a processing temperature of 650° C.˜700° C. and a nitrogen containing gas annealing process with a processing temperature of 900° C.˜1000° C. are sequentially performed on the barrier layer. The present invention also provides a semiconductor process including the following steps. A dielectric layer is formed on a substrate. A first nitrogen containing thermal treatment process is performed on the dielectric layer. A barrier layer is formed on the dielectric layer. A second nitrogen containing thermal treatment process and then an annealing process are performed in-situ on the barrier layer.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成电介质层。 在电介质层上形成阻挡层。 在阻挡层上依次进行处理温度为650℃〜700℃的氨热处理工序和处理温度为900℃〜1000℃的含氮气体退火处理。 本发明还提供一种包括以下步骤的半导体工艺。 在基板上形成电介质层。 在介电层上进行第一含氮热处理工艺。 在电介质层上形成阻挡层。 在阻挡层上原位进行第二种含氮热处理工艺，然后进行退火处理。

公开(公告)号：US09431483B1

公开(公告)日：2016-08-30

申请号：US14658262

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US09349599B1

公开(公告)日：2016-05-24

申请号：US14537827

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Feng Ku ,  Shao-Wei Wang ,  Yi-Hui Lin ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/28035

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，其中栅极结构包括高k电介质层; 通过注入第一气体将栅极结构周围的环境压力增加到预定压力; 将环境压力降低到基础压力; 以及在所述栅极结构周围形成间隔物。