公开(公告)号：US09391174B1

公开(公告)日：2016-07-12

申请号：US14730735

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/3083

Abstract: Uniform fin recessing for the situation of recessing nonadjacent fins and the situation of recessing adjacent fins includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple fins coupled to the substrate, each fin having a hard mask layer thereover and being surrounded by isolation material. The hard mask layer is then removed over some of the fins, at least partially removing the some of the raised structures, the at least partially removing creating openings, and filling the openings with an optical planarization layer (OPL) material.

Abstract translation: 针对不相邻散热片的凹陷状况的均匀的翅片凹陷以及相邻散热片的凹陷情况包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个鳍片，每个散热片具有其上的硬掩模层并被 隔离材料。 然后在一些翅片上去除硬掩模层，至少部分地去除一些凸起结构，至少部分去除创建开口，并用光学平坦化层（OPL）材料填充开口。

公开(公告)号：US20160190339A1

公开(公告)日：2016-06-30

申请号：US15065998

申请日：2016-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ajey Poovannummoottil Jacob

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.

Abstract translation: 半导体器件包括源极/漏极区域，栅极结构，位于栅极结构上方的栅极盖层和邻近栅极结构的相对侧定位的侧壁间隔物。 第一外延半导体材料位于源极/漏极区域中，第一外延半导体材料在其上表面具有第一横向宽度。 第二外延半导体材料定位在第一外延半导体材料上，第二外延半导体材料横向延伸并覆盖侧壁间隔物的最上端的至少一部分，并且在其上表面具有更大的第二横向宽度 比第一横向宽度。 金属硅化物区域位于第二外延半导体材料的上表面上。

公开(公告)号：US20160190306A1

公开(公告)日：2016-06-30

申请号：US15063633

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L2029/7858

Abstract: One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

Abstract translation: 本文公开的一个说明性装置尤其包括半导体衬底，翅片结构，位于器件的沟道区域中的翅片结构的一部分周围的栅极结构，第二半导体材料的间隔开的部分位于 所述翅片结构和所述基板，其中所述第二半导体材料是与所述翅片不同的半导体材料，以及局部通道隔离材料，其横向位于所述第二半导体材料的所述间隔开的部分之间并且垂直于所述翅片结构的下方， 栅极结构，其中所述局部沟道隔离材料位于所述器件的沟道区域的至少一部分的下方。

公开(公告)号：US20160163601A1

公开(公告)日：2016-06-09

申请号：US14560102

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

公开(公告)号：US20160163585A1

公开(公告)日：2016-06-09

申请号：US14674460

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

公开(公告)号：US09349598B2

公开(公告)日：2016-05-24

申请号：US14832530

申请日：2015-08-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US20160133623A1

公开(公告)日：2016-05-12

申请号：US14536243

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Andre Labonte ,  Su Chen Fan ,  Balasubramanian S. Pranatharthi Haran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/528 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.

Abstract translation: 本文公开的一种方法包括在凹陷的最终栅极结构上方和在凹陷的侧壁间隔物之上形成栅极盖层，形成导电耦合到第一源极/漏极区域的凹陷沟槽硅化物区域，凹陷沟槽硅化物区域 具有位于所述侧壁间隔物的凹陷的上表面下方的水平面的上表面，在暴露所述凹入的最终栅极结构的导电部分的至少一层材料中形成组合的接触开口， 沟槽硅化物区域，并且在组合的接触开口中形成组合的栅极和源极/漏极接触结构。

公开(公告)号：US20160118385A1

公开(公告)日：2016-04-28

申请号：US14981574

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Su Chen Fan ,  Shom Ponoth

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: A transistor device includes a gate structure positioned above a semiconductor substrate and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure, wherein an internal sidewall surface of each of the spaced-apart sidewall spacers has a stepped cross-sectional configuration

Abstract translation: 晶体管器件包括位于半导体衬底上方的栅极结构和位于衬底上方的间隔开的侧壁隔离物和栅极结构的相邻侧壁，其中每个间隔开的侧壁间隔件的内侧壁表面具有阶梯状横截面 组态

公开(公告)号：US09318388B2

公开(公告)日：2016-04-19

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20160104644A1

公开(公告)日：2016-04-14

申请号：US14512700

申请日：2014-10-13

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract translation: 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。