公开(公告)号：US09627381B1

公开(公告)日：2017-04-18

申请号：US14969678

申请日：2015-12-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/00 ,  H01L27/092 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/167 ,  H01L21/265 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165

Abstract: Techniques for effectively confining n-well dopants during fabrication of relaxed SiGe on SRB devices are provided. In one aspect, a method for forming a semiconductor device includes the steps of: forming a SiGe stress relief buffer layer on a substrate; growing a bottom confinement layer on the stress relief buffer layer; growing a SiGe layer on the bottom confinement layer; growing a top confinement layer on the SiGe layer; forming STI regions extending through the top confinement layer, through the SiGe layer, and at least down to the bottom confinement layer, wherein the STI regions define at least one active area in the SiGe layer; and implanting at least one well dopant into the at least one active area which is confined to the at least one active area by the top confinement layer, the bottom confinement layer, and the STI regions. A semiconductor device is also provided.

公开(公告)号：US20170092736A1

公开(公告)日：2017-03-30

申请号：US15220723

申请日：2016-07-27

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings.

公开(公告)号：US20170084492A1

公开(公告)日：2017-03-23

申请号：US15070437

申请日：2016-03-15

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/306 ,  H01L29/423 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823425 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

公开(公告)号：US20170077232A1

公开(公告)日：2017-03-16

申请号：US14851584

申请日：2015-09-11

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7853 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A method for manufacturing a semiconductor device comprises epitaxially growing a plurality of silicon layers and compressively strained silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and compressively strained SiGe layers are alternately stacked on each other starting with a silicon layer on a bottom of the stacked configuration, patterning the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width less than the first width, forming an oxide layer on the compressively strained SiGe layers of the stacked configuration, wherein forming the oxide layer comprises fully oxidizing the silicon layers so that portions of the oxide layer are formed in place of each fully oxidized silicon layer, and removing part of the oxide layer while maintaining at least part of the portions of the oxide layer formed in place of each fully oxidized silicon layer, wherein the compressively strained SiGe layers are anchored to one another and a compressive strain is maintained in each of the compressively strained SiGe layers.

Abstract translation: 一种半导体器件的制造方法，其特征在于，在层叠结构的基板上外延生长多个硅层和压缩应变硅锗（SiGe）层，其中，硅层和压缩应变SiGe层从 在层叠结构的底部形成硅层，将层叠结构图案化为第一宽度，以层叠结构选择性地去除每个硅层的一部分，以将硅层减小到小于第一宽度的第二宽度，从而形成 形成氧化物层的压缩应变SiGe层上的氧化物层包括完全氧化硅层，以形成氧化物层的一部分代替每个完全氧化的硅层，并且除去氧化物层的一部分同时 保持形成的氧化物层的至少一部分代替各自的部分 完全氧化的硅层，其中压缩应变的SiGe层相互锚定并且压缩应变保持在每个压缩应变的SiGe层中。

公开(公告)号：US20170033017A1

公开(公告)日：2017-02-02

申请号：US15144136

申请日：2016-05-02

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823807 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/7849

Abstract: A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.

Abstract translation: 一种方法包括形成由第一半导体材料构成的一组鳍片。 该方法进一步加热翅片集合以使翅片冷凝并引起其垂直侧壁上的一层氧化物的生长，掩蔽散热片的第一子组，通过除去第二子组而在氧化物中形成多个空隙 的翅片，其中每个空隙具有三维形状和尺寸，其对应于来自第二子组的相应的去除翅片的三维形状和尺寸，并且在空隙中外延生长第三子鳍组。 翅片的第三子组由与第一半导体材料不同的第二半导体材料组成。 第三子集的每个鳍具有来自第二子集的相应的去除翅片的三维形状和尺寸。 还公开了通过该方法形成的至少一种结构。

公开(公告)号：US20170018508A1

公开(公告)日：2017-01-19

申请号：US14798007

申请日：2015-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L23/00 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US20160359037A1

公开(公告)日：2016-12-08

申请号：US14729464

申请日：2015-06-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L21/823431 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.

公开(公告)号：US20160329326A1

公开(公告)日：2016-11-10

申请号：US14704760

申请日：2015-05-05

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/223

CPC classification number: H01L27/0886 ,  H01L21/223 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66803

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a hard mask, in a fin layer on a semiconductor wafer and spaces between the pedestals are filled with dielectric material, e.g., shallow trench isolation (STI). Sacrificial sidewalls are forming along the sides of fins and pedestal sub-fins sidewalls are re-exposed. Pedestal sub-fins are doped with a punch-though dopant and punch-though dopant is diffused into the sub-fins and the bottoms of fins. After removing the hard mask and sacrificial sidewalls, metal FET gates are formed on the fins.

Abstract translation: 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成IC的方法。 在半导体晶片上的翅片层中，例如用硬掩模来限定基座上的金属丝，并且在基座之间的间隔填充介电材料，例如浅沟槽隔离（STI）。 牺牲侧壁沿着翅片的侧面形成，并且底座副翅片侧壁被再次暴露。 基座子散热片掺杂有穿孔掺杂剂，穿孔掺杂剂扩散到散热片的散热片和散热片底部。 在去除硬掩模和牺牲侧壁之后，在翅片上形成金属FET栅极。

公开(公告)号：US09472671B1

公开(公告)日：2016-10-18

申请号：US14929312

申请日：2015-10-31

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/161

Abstract: A semiconductor structure and method for fabricating such. The semiconductor structure includes a monolithic substrate, a first dielectric layer carried by the monolithic substrate and a second dielectric layer carried by the monolithic substrate. The first dielectric layer has a first Young's modulus, and the second dielectric layer has a second Young's modulus. The first Young's modulus is at least twice the second Young's modulus. A compressive SiGe layer is positioned over and in contact with the first dielectric layer. A relaxed SiGe layer is positioned over and in contact with the second dielectric layer. The relaxed SiGe layer is spaced apart from the compressive SiGe layer.

Abstract translation: 一种半导体结构及其制造方法。 半导体结构包括单片基板，由整体式基板承载的第一电介质层和由整体式基板承载的第二电介质层。 第一介电层具有第一杨氏模量，第二介电层具有第二杨氏模量。 第一杨氏模量至少是第二杨氏模量的两倍。 压缩SiGe层位于第一介电层上并与其接触。 放松的SiGe层位于第二介电层上并与其接触。 松弛的SiGe层与压缩SiGe层间隔开。

公开(公告)号：US09443982B1

公开(公告)日：2016-09-13

申请号：US15018066

申请日：2016-02-08

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78642 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor structure containing a vertical transistor having air gap spacers located above and below each functional gate structure is provided. Notably, a bottom air gap spacer is located between a bottommost surface of first and second functional gate structures and a topmost surface of a bottom source/drain region, and a top air gap spacer is located between a topmost surface of the first and second functional gate structures and a surface of the top source/drain region.

Abstract translation: 提供了一种包含位于每个功能栅极结构之上和之下的具有气隙间隔物的垂直晶体管的半导体结构。 值得注意的是，底部气隙间隔件位于第一和第二功能门结构的最底表面与底部源极/漏极区域的最上表面之间，顶部气隙间隔件位于第一和第二功能栅极结构的最上表面之间 栅极结构和顶部源极/漏极区域的表面。