公开(公告)号：US10269805B2

公开(公告)日：2019-04-23

申请号：US15895928

申请日：2018-02-13

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Chandra Mouli ,  Sanh D. Tang

IPC: G11C5/02 ,  G11C5/06 ,  H01L27/108 ,  H01L29/78

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

公开(公告)号：US20190006387A1

公开(公告)日：2019-01-03

申请号：US16125242

申请日：2018-09-07

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/11582 ,  G11C13/00 ,  H01L27/06 ,  H01L27/11565 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11548 ,  H01L21/28 ,  H01L27/24

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US20180226427A1

公开(公告)日：2018-08-09

申请号：US15945215

申请日：2018-04-04

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09865812B2

公开(公告)日：2018-01-09

申请号：US15375457

申请日：2016-12-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L21/768 ,  H01L45/00 ,  H01L23/532

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

公开(公告)号：US20170365614A1

公开(公告)日：2017-12-21

申请号：US15691442

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/11556 ,  H01L29/792 ,  H01L29/788 ,  H01L29/49 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11524 ,  H01L29/04 ,  H01L29/167

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

公开(公告)号：US20170317099A1

公开(公告)日：2017-11-02

申请号：US15651916

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09761590B1

公开(公告)日：2017-09-12

申请号：US15162028

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L23/52 ,  H01L27/108 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  G11C11/4078

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/404 ,  G11C11/4078 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

公开(公告)号：US20170243921A1

公开(公告)日：2017-08-24

申请号：US15497032

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Sanh D. Tang ,  David H. Wells

IPC: H01L27/24 ,  H01L29/78 ,  H01L29/66 ,  H01L45/00 ,  H01L29/45

CPC classification number: H01L27/2454 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/2463 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

公开(公告)号：US20170213761A1

公开(公告)日：2017-07-27

申请号：US15481301

申请日：2017-04-06

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Ming Zhang

IPC: H01L21/762 ,  H01L29/861 ,  H01L27/08 ,  H01L21/32

CPC classification number: H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.

公开(公告)号：US20170117292A1

公开(公告)日：2017-04-27

申请号：US15397919

申请日：2017-01-04

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.