公开(公告)号：US20240079278A1

公开(公告)日：2024-03-07

申请号：US18151061

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Yong Han ,  Wen-Yen Chen ,  Yi-Ting Wu ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/0928 ,  H01L21/266

Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.

公开(公告)号：US20240072128A1

公开(公告)日：2024-02-29

申请号：US18502183

申请日：2023-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/40 ,  H01L21/033 ,  H01L21/285 ,  H01L21/3115 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/0337 ,  H01L21/28518 ,  H01L21/31155 ,  H01L29/456

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

公开(公告)号：US11908708B2

公开(公告)日：2024-02-20

申请号：US17479467

申请日：2021-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/50

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

公开(公告)号：US11855146B2

公开(公告)日：2023-12-26

申请号：US17648156

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/324

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US11848361B2

公开(公告)日：2023-12-19

申请号：US17651843

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/40 ,  H01L29/45 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/285

CPC classification number: H01L29/401 ,  H01L21/0337 ,  H01L21/28518 ,  H01L21/31155 ,  H01L29/456

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

公开(公告)号：US11842933B2

公开(公告)日：2023-12-12

申请号：US17150018

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Yu Huang ,  Han-De Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764

CPC classification number: H01L21/823878 ,  H01L21/764 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

公开(公告)号：US20230369103A1

公开(公告)日：2023-11-16

申请号：US18359414

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76822 ,  H01L23/5283 ,  H01L21/76883 ,  H01L23/53295 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53242 ,  H01L21/76886

Abstract: A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

公开(公告)号：US11776810B2

公开(公告)日：2023-10-03

申请号：US17463000

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US11705505B2

公开(公告)日：2023-07-18

申请号：US17818400

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/764 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4991 ,  H01L29/515 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L21/0228 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

公开(公告)号：US11646377B2

公开(公告)日：2023-05-09

申请号：US17223600

申请日：2021-04-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/7856 ,  H01L21/823418 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818

Abstract: In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.