公开(公告)号：US20180301194A1

公开(公告)日：2018-10-18

申请号：US15956647

申请日：2018-04-18

Applicant: Rambus Inc.

Inventor： Brent S. Haukness ,  Ian Shaeffer ,  Gary Bela Bronner

IPC: G11C16/10 ,  G06F3/06

Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

公开(公告)号：US10026466B2

公开(公告)日：2018-07-17

申请号：US15616209

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US10014860B2

公开(公告)日：2018-07-03

申请号：US15629265

申请日：2017-06-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  H03K19/0175 ,  G11C11/4063 ,  G11C11/413

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20180137909A1

公开(公告)日：2018-05-17

申请号：US15832468

申请日：2017-12-05

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4096 ,  G06F13/40

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20180137902A1

公开(公告)日：2018-05-17

申请号：US15794177

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC: G11C7/22 ,  G11C29/56 ,  G11C29/50 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US20180047436A1

公开(公告)日：2018-02-15

申请号：US15623261

申请日：2017-06-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/02 ,  G11C7/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20170371827A1

公开(公告)日：2017-12-28

申请号：US15647983

申请日：2017-07-12

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G06F13/16 ,  G11C11/4094 ,  G11C11/4093 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US09721629B2

公开(公告)日：2017-08-01

申请号：US15394009

申请日：2016-12-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

公开(公告)号：US09652409B2

公开(公告)日：2017-05-16

申请号：US14871754

申请日：2015-09-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F13/16 ,  G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1458 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20160373111A1

公开(公告)日：2016-12-22

申请号：US15187861

申请日：2016-06-21

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: H03K19/00 ,  G11C5/14 ,  H03K19/0175

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.